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7306991 Stepped gate configuration for non-volatile memory  
A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor...
7307027 Void free interlayer dielectric  
A method of forming a dielectric between memory cells in a device includes forming multiple memory cells, where a gap is formed between each of the multiple memory cells. The method further...
7306990 Information storage element, manufacturing method thereof, and memory array  
An information memory device capable of reading and writing of information by mechanical operation of a floating gate layer, in which a gate insulation film has a cavity ( 6 ), and a floating gate...
7303957 Method of fabricating a flash memory device  
A method of fabricating a flash memory device using a process for forming a self-aligned floating gate is provided. The method comprises forming mask patterns on a substrate, etching the substrate...
7303955 Semiconductor memory device with high operating current and method of manufacturing the same  
In a semiconductor memory device with a high operating current and a method of manufacturing the same, a semiconductor substrate is formed in which a memory cell region and a peripheral circuit...
7304344 Integrated circuit having independently formed array and peripheral isolation dielectrics  
The invention comprises a method of forming an integrated circuit, the method comprising: (1) forming a first dielectric layer disposed outwardly from a semiconductor substrate; (2) forming a first...
7303954 Method for manufacturing NAND flash device  
Disclosed is a method for manufacturing a NAND flash device. After a source line plug hole is formed, a drain contact plug hole is formed. The holes are filled with a conductive material film and...
7303950 Semiconductor device, method of manufacturing same and method of designing same  
A partial oxide film ( 31 ) with well regions formed therebeneath isolates transistor formation regions in an SOI layer ( 3 ) from each other. A p-type well region ( 11 ) is formed beneath part of...
7300888 Methods of manufacturing integrated circuit devices having an encapsulated insulation layer  
An integrated circuit device is manufactured by forming an insulating layer on a substrate. A capping layer is formed on the insulating layer and both the capping layer and the insulating layer are...
7300745 Use of pedestals to fabricate contact openings  
Nonvolatile memory wordlines ( 160 ) are formed as sidewall spacers on sidewalls of control gate structures ( 280 ). Each control gate structure may contain floating and control gates ( 120, 140 ),...
7300842 Method of fabricating a mask ROM  
A mask ROM and fabrication method thereof are disclosed, in which a bit line is formed of a conductive material such as polysilicon, by which a device size can be minimized, and by which resistance...
7300844 Method of forming gate of flash memory device  
A method of forming a gate of a flash memory device, including the steps of forming a tunnel oxide film and a first polysilicon layer in an active region of a semiconductor substrate, an isolation...
7297593 Method of manufacturing a floating gate of a flash memory device  
A method of forming a floating gate of a flash memory device wherein a hard mask nitride film is stripped using two or more etching steps. Accordingly, a seam can be prevented when depositing a...
7298005 Nonvolatile semiconductor memory and fabrication method for the same  
A nonvolatile semiconductor memory includes a first and a second active area configured to extend in the column direction in parallel; an element isolating region configured to electrically...
7297598 Process for erase improvement in a non-volatile memory device  
A method of making embedded non-volatile memory devices includes forming a first mask layer overlying a polycrystalline silicon layer in a cell region and a peripheral region on a semiconductor...
7297592 Semiconductor memory with data retention liner  
A manufacturing method for a dual bit flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer with the depositing performed without using ammonia...
7294547 SONOS memory cell having a graded high-K dielectric  
A semiconductor memory device may include an intergate dielectric layer of high-K dielectric materials interposed between a charge storing layer and a control gate. The high-K materials may be...
7288455 Method of forming non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors  
Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench...
7285463 Method of fabricating non-volatile memory  
A method of fabricating a non-volatile memory is described. A plurality of first memory units having gaps between each other is formed over a substrate. Insulating spacers are formed on the...
7285815 EEPROM device having selecting transistors and method of fabricating the same  
An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that...
7285811 MRAM device for preventing electrical shorts during fabrication  
The present invention provides an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor is provided in a trench in an insulating layer and an upper...
7282409 Isolation structure for a memory cell using Al2O3 dielectric  
The invention provides, in one exemplary embodiment, an isolation gate formed over a substrate for biasing the substrate and providing isolation between adjacent active areas of an integrated...
7282411 Method of manufacturing a nonvolatile semiconductor memory device  
An AND flash memory of the type wherein a memory cell is constituted of n-type semiconductor regions (a source and a drain) formed in a p-type well of a semiconductor substrate and three gates...
7279384 Semiconductor memory and method for manufacturing the same  
A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a P type silicon substrate, a control gate CG and a pair of electrically isolated...
7279394 Method for forming wall oxide layer and isolation layer in flash memory device  
Disclosed herein are methods for forming wall oxide films in flash memory devices and methods for forming isolation films. After trenches are formed in the substrate, an ISSG (In-Situ Steam...
7279738 Semiconductor device with an analog capacitor  
A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon...
7279342 Ferroelectric memory  
A ferroelectric memory includes a base member, a first dielectric layer formed above the base member, a second dielectric layer formed above the first dielectric layer, a contact hole that...
7276733 Select lines for NAND memory devices  
A NAND memory array has a select line coupled to each of a plurality of NAND strings of memory cells of the memory array. The select line has a select gate at each intersection of one of the...
7276755 Integrated circuit and method of manufacture  
An integrated circuit having a plurality of active areas separated from each other by a field region and a method for manufacturing the integrated circuit. A first polysilicon finger is formed over...
7276384 Magnetic tunnel junctions with improved tunneling magneto-resistance  
A magnetic tunnel element that can be used, for example, as part of a read head or a magnetic memory cell, includes a first layer formed from an amorphous material, an amorphous tunnel barrier...
7273782 Method for manufacturing and operating a non-volatile memory  
A method for manufacturing and operating a nonvolatile memory in which a floating gate is formed on a silicon substrate to reduce the difference in heights between a memory region and a logic...
7273775 Reliable and scalable virtual ground memory array formed with reduced thermal cycle  
According to one exemplary embodiment, a method of fabricating a virtual ground memory array includes forming a number of polysilicon segments on a gate dielectric layer, where the gate dielectric...
7271438 Self-aligned silicide for word lines and contacts  
An embodiment of a floating-gate memory cell has a tunnel dielectric layer formed overlying a semiconductor substrate; a drain region formed in a semiconductor substrate adjacent a first side of...
7271061 Method of fabricating non-volatile memory  
In one embodiment, a semiconductor device includes a semiconductor substrate having a first junction region and a second junction region. An insulated floating gate is disposed on the substrate....
7271060 Semiconductor processing methods  
The invention includes methods in which common processing steps are utilized during fabrication of components of a memory array region of a semiconductor substrate and components of a peripheral...
7271063 Method of forming FLASH cell array having reduced word line pitch  
A method of forming a NAND Flash memory device includes forming a control gate polysilicon layer over a substrate, forming a mask layer over the control gate polysilicon layer, the mask layer...
7271062 Non-volatile memory cell and fabricating method thereof and method of fabricating non-volatile memory  
A method of fabricating a non-volatile memory is provided. In the fabricating method, a plurality of stack gate structures is formed on a substrate and a plurality of doped regions is formed in the...
7268040 Method of manufacturing a select transistor in a NAND flash memory  
Disclosed herein is a method of manufacturing a flash memory device. According to the present invention, a method of manufacturing a NAND flash memory device having a memory cell and a select...
7268046 Dual gate oxide high-voltage semiconductor device and method for forming the same  
A dual gate oxide high-voltage semiconductor device and method for forming the same are provided. Specifically, a device formed according to the present invention includes a semiconductor...
7268055 Method of fabricating semiconductor device  
A method of fabricating a semiconductor device is provided. Before covering the isolation structures with a conductive layer, a material layer is formed on the isolation structures. The fluid-like...
7268064 Method of forming polysilicon layer in semiconductor device  
Disclosed herein is a method of forming a polysilicon film of a semiconductor device. Upon deposition process of a polysilicon film, the inflow of a gas is reduced to 150 sccm to 250 sccm to...
7265376 Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell  
A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor...
7265015 Use of chlorine to fabricate trench dielectric in integrated circuits  
Chlorine is incorporated into pad oxide ( 110 ) formed on a silicon substrate ( 120 ) before the etch of substrate isolation trenches ( 134 ). The chlorine enhances the rounding of the top corners...
7265014 Avoiding field oxide gouging in shallow trench isolation (STI) regions  
A method and device for avoiding oxide gouging in shallow trench isolation (STI) regions of a semiconductor device. A trench may be etched in an STI region and filled with insulating material. An...
7262095 System and method for reducing process-induced charging  
A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise...
7262096 NAND flash memory cell row and manufacturing method thereof  
A NAND flash memory cell row includes first and second stacked gate structures, control and floating gates, inter-gate dielectric layer, a tunnel oxide layer, doping regions and source/drain...
7262093 Structure of a non-volatile memory cell and method of forming the same  
A flash memory cell is provided. The flash memory cell includes a substrate having a source and a drain formed therein, a bit line contact formed above the drain, a control gate formed above the...
7262097 Method for forming floating gate in flash memory device  
A method for fabricating a nonvolatile memory device including successively forming a first oxide layer, an electrically conductive layer, a second oxide layer, a nitride layer and a third oxide...
7259067 Method for manufacturing flash memory device  
The present invention relates to a method for manufacturing a flash memory device. A plurality of conductive layers and dielectric layers are etched in a single etch apparatus, thus forming a...
7259062 Method of making a magnetic tunnel junction device  
A method of making a magnetic tunnel junction device is disclosed. The magnetic tunnel junction device includes a magnetic tunnel junction stack and an electrically non-conductive spacer in contact...
Matches 401 - 450 out of 1787 < 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 >