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7060561 |
Method for fabricating memory device
The present invention relates to a method for fabricating a memory device. According to this invention, because the trenches for the isolation structures are etched simultaneously as patterning the...
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7060558 |
Method for fabricating a field-effect transistor having a floating gate
In the course of a method for fabricating a field-effect transistor having a floating gate, a structure is formed which has uncovered sidewalls of a layer made of the material for forming the...
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7060581 |
Method for manufacturing a semiconductor device
A method for manufacturing a semiconductor device, includes forming a first impurity implanted layer in a semiconductor substrate by selectively implanting ions of a first impurity. A dummy pattern...
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7060560 |
Method of manufacturing non-volatile memory cell
A method of manufacturing a non-volatile memory cell includes forming a first dielectric layer on a substrate. A second dielectric layer having a trench is formed on the first dielectric layer....
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7061034 |
Magnetic random access memory including middle oxide layer and method of manufacturing the same
In a magnetic random access memory (MRAM) having a transistor and a magnetic tunneling junction (MTJ) layer in a unit cell, the MTJ layer includes a lower magnetic layer, an oxidation preventing...
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7056790 |
DRAM cell having MOS capacitor and method for manufacturing the same
A DRAM cell having a MOS capacitor and a method for manufacturing the same are disclosed. The DRAM cell includes: an active region of a semiconductor substrate; a MOS capacitor consisting of a...
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7056816 |
Method for manufacturing semiconductor device
A mask layer having an opening is formed on a semiconductor substrate. Next, oxygen ions and a first impurity are implanted into the semiconductor substrate using the mask layer as a mask. Then,...
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7056789 |
Production method for semiconductor substrate and production method for field effect transistor and semiconductor substrate and field effect transistor
The present invention relates to a semiconductor substrate production method, field effect transistor production method, semiconductor substrate and field effect transistor which, together with...
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7056785 |
Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same
A non-volatile memory cell is fabricated using a conventional logic process, with minor modifications. The cell is fabricated by forming a shallow trench isolation (STI) region in a well region of...
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7052958 |
FinFET CMOS with NVRAM capability
The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having Non-Volatile Random Access Memory (NVRAM) capability. NVRAM...
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7053438 |
Fabrication of gate dielectric in nonvolatile memories in which a memory cell has multiple floating gates
In fabrication of a nonvolatile memory cell having two floating gates, one or more peripheral transistor gates are formed from the same layer ( 140 ) as the select gate. The gate dielectric ( 130 )...
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7052947 |
Fabrication of gate dielectric in nonvolatile memories in which a memory cell has multiple floating gates
In fabrication of a nonvolatile memory cell having two floating gates, one or more peripheral transistor gates are formed from the same layer ( 140 ) as the select gate. The gate dielectric ( 130 )...
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7053442 |
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device having a small layout area includes a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction. The...
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7052954 |
Method of fabricating a MOS structure with two conductive layers on the gate electrode
A gate electrode < 13 > is provided to fill up a trench < 300 > while covering its opening. Assuming that W G represents the diameter (sectional width) of a head portion of the gate...
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7049215 |
Thin film transistor array panel and fabricating method thereof
A method of forming a thin film transistor array panel is described. The thin film transistor array comprises a substrate, a plurality of scan lines, a plurality of gates a plurality of first...
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7045421 |
Process for making bit selectable devices having elements made with nanotubes
A method is used to make a bit selectable device having nanotube memory elements. A structure having at least two transistors is provided, each with a drain and a source with a defined channel...
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7045420 |
Semiconductor device comprising capacitor and method of fabricating the same
A high density semiconductor device is formed with a constant capacitor capacitance. The semiconductor device includes a memory cell region and a peripheral circuit region. An insulating film,...
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7045419 |
Elimination of the fast-erase phenomena in flash memory
A method of forming a semiconductor device that includes providing a semiconductor substrate, forming a first insulating layer over the semiconductor substrate, forming a floating gate over the...
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7045418 |
Semiconductor device including a dielectric layer having a gettering material located therein and a method of manufacture therefor
The present invention provides a semiconductor device ( 200 ), a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the semiconductor...
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7045422 |
Semiconductor gate structure and method for fabricating a semiconductor gate structure
A method for fabricating a semiconductor gate structure including depositing at least one sacrificial layer on a semiconductor substrate; patterning the at least one sacrificial layer to form at...
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7042066 |
Dual-trench isolated crosspoint memory array
A memory array dual-trench isolation structure and a method for forming the same have been provided. The method comprises: forming a p-doped silicon (p-Si) substrate; forming an n-doped (n+) Si...
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7037784 |
Method of forming floating gate electrode of flash memory device
The present invention relates to a method of forming a floating gate electrode of a flash memory device. According to the present invention, the method includes the steps of forming a first silicon...
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7037574 |
Atomic layer deposition for fabricating thin films
An atomic layer deposition (ALD) process deposits thin films for microelectronic structures, such as advanced gap and tunnel junction applications, by plasma annealing at varying film thicknesses...
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7037782 |
Semiconductor memory having storage cells storing multiple bits and a method of manufacturing the same
A multiple-bit cell transistor includes a P type silicon substrate, a gate insulation layer, a pair of N type source/drain regions, a pair of tunnel insulation layers, and a pair of floating gates....
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7037786 |
Method of forming a low voltage gate oxide layer and tunnel oxide layer in an EEPROM cell
A method of fabricating a non-volatile memory embedded logic circuit having a low voltage logic gate oxide layer and tunnel oxide layer is described. Both the low voltage logic gate oxide and the...
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7037779 |
Semiconductor device and manufacturing method thereof
In a thin film transistor, a metallic element promoting crystallization of an amorphous silicon film is effectively removed and the productivity is improved. By using a silicon film containing an...
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7038231 |
Non-planarized, self-aligned, non-volatile phase-change memory array and method of formation
A method for fabrication and a structure of a self-aligned (crosspoint) memory device comprises lines (wires) in a first direction and in a second direction. The wires in the first direction are...
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7037785 |
Method of manufacturing flash memory device
Disclosed is a method of manufacturing the flash memory device. The method comprises the steps of sequentially forming a tunnel oxide film, a first polysilicon film and a hard mask film on a...
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7033888 |
Engineered metal gate electrode
A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric...
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7034354 |
Semiconductor structure with lining layer partially etched on sidewall of the gate
A semiconductor structure with partially etched gate and method of fabricating the same. A semiconductor structure with a single-sided or dual-sided partially etched gate comprises a gate...
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7029973 |
Method of fabricating a flash memory cell
A method of forming a flash memory cell. A tunnel oxide layer, a floating gate layer, and a dielectric layer are formed on a substrate. A control gate layer is formed on the dielectric layer and...
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7029968 |
Method of forming a PIP capacitor
A method of forming a polysilicon-insulator-polysilicon (PIP) capacitor in a mixed mode semiconductor device. A floating gate of a split gate transistor and a bottom electrode of a PIP capacitor...
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7026216 |
Method for fabricating nitride read-only memory
A method for fabricating a nitride read-only memory is described. An ONO stacked layer and a protective layer are sequentially formed on a substrate. A patterning/etching process is performed to...
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7026687 |
Non-volatile semiconductor memory and method of manufacturing the same
A proposed non-volatile semiconductor memory and a method of manufacturing the same are directed to performing stable and highly reliable operations. First, grooves are formed in a p-type silicon...
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7027328 |
Integrated circuit memory device and method
Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region...
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7026212 |
Method for making high density nonvolatile memory
An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing;...
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7026211 |
Semiconductor component and method of manufacture
A semiconductor component having smooth, void-free conductive layers and a method for manufacturing the semiconductor component. Surface features such as gate structures are formed on a...
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7022573 |
Stack gate with tip vertical memory and method for fabricating the same
A stacked gate vertical flash memory and a fabrication method thereof. The stacked gate vertical flash memory comprises a semiconductor substrate with a trench, a source conducting layer formed on...
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7022571 |
Quantum structure and forming method of the same
A quantum structure and the forming method based on the difference in characteristic of two matters is provided. The forming method includes several steps. At first, providing a first dielectric...
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7022572 |
Manufacturing method for integrated circuit having disturb-free programming of passive element memory cells
In a passive element memory array, such as a rail stack array having a continuous semiconductor region along one or both of the array lines, programming a memory cell may disturb nearby memory...
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7023043 |
Top electrode in a strongly oxidizing environment
An improved charge storing device and methods for providing the same, the charge storing device comprising a conductor-insulator-conductor (CIC) sandwich. The CIC sandwich comprises a first...
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7023047 |
MOS device and process for manufacturing MOS devices using dual-polysilicon layer technology
An MOS device has a stack and a passivation layer covering the stack. The stack is formed by a first polysilicon region and by a second polysilicon region arranged on top of one another and...
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7023045 |
Layout of a flash memory having symmetric select transistors
A layout of flash memory having symmetric select transistors includes a memory cell array and a polysilicon gate. The polysilicon gate forms a plurality of select transistors in coordination with a...
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7018895 |
Nonvolatile memory cell with multiple floating gates formed after the select gate
In a memory cell ( 110 ) having multiple floating gates ( 160 ), the select gate ( 140 ) is formed before the floating gates. In some embodiments, the memory cell also has control gates ( 170 )...
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7018894 |
EEPROM device having selecting transistors and method of fabricating the same
An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that...
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7015096 |
Bimetallic oxide compositions for gate dielectrics
In one embodiment, bimetallic oxide compositions for gate dielectrics that include two or more of the elements Ca, Sr, Ba, Hf, and Zr are described.
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7015100 |
Method of fabricating one-time programmable read only memory
A method of fabricating a one-time programmable read only memory of the present invention is provided. First, a substrate having a memory cell area and a peripheral circuit area is provided. The...
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7015095 |
Method for fabricating a semiconductor memory having charge trapping memory cells and semiconductor substrate
Electrically conductive material is introduced into interspaces between the word lines ( 2 ) and is partially removed using a mask ( 6 ) in such a way that residual portions ( 7 ) of the conductive...
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7015099 |
Method of manufacturing a flash memory cell capable of increasing a coupling ratio
A method of manufacturing a flash memory cell. The method includes controlling a wall sacrificial oxidization process, a wall oxidization process and a cleaning process of a trench insulating film...
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7015098 |
Methods and structure for an improved floating gate memory cell
A method and structure for an improved floating gate memory cell are provided. The non volatile memory cell includes a substrate and a first insulating layer formed on the substrate. The memory...
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