Matches 301 - 350 out of 1043 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
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6979608 Method of manufacturing an on-chip inductor having improved quality factor  
An on-chip inductor may be fabricated by creating at least one dielectric layer, creating at least one conductive winding on the at least one dielectric layer and creating: (1) a P-well layer...
6977196 Micro-electromechanical switch fabricated by simultaneous formation of a resistor and bottom electrode  
The present invention provides a method and product-by-method of integrating a bias resistor in circuit with a bottom electrode of a micro-electromechanical switch on a silicon substrate. The...
6974708 Oxidation structure/method to fabricate a high-performance magnetic tunneling junction MRAM  
An MTJ (magnetic tunneling junction) MRAM (magnetic random access memory) has a tunneling barrier layer of substantially uniform and homogeneous Al 2 O 3 stoichiometry. The barrier layer is formed...
6974743 Method of making encapsulated spacers in vertical pass gate DRAM and damascene logic gates  
Semiconductor devices having improved isolation are provided along with methods of fabricating such semiconductor devices. The improved isolation includes an encapsulated spacer formed within a...
6967134 Methods of forming nitrogen-containing masses, silicon nitride layers, and capacitor constructions  
The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass...
6964895 Method of fabricating vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region  
A vertical one-transistor, floating-body DRAM cell is fabricated by forming an isolation region in a semiconductor substrate, thereby defining a semiconductor island in the substrate. A buried...
6962875 Variable contact method and structure  
A method of forming a variable contact structure, and the structure so formed, comprising forming a via within the device, wherein a diameter of the via is variably determined depending upon the...
6960479 Stacked ferroelectric memory device and method of making same  
The present invention relates to a ferroelectric polymer storage device including at least two stacked ferroelectric polymer memory structures that are arrayed next to at least two respective...
6958246 Methods of forming magnetoresistive memory devices  
The invention includes a magnetoresistive memory device having a conductive core, and a first magnetic layer extending at least partially around the conductive core. A non-magnetic material is over...
6955959 Method of making a memory structure having a multilayered contact and a storage capacitor with a composite dielectric layer of crystalized niobium pentoxide and tantalum pentoxide films  
The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization...
6953720 Methods for forming chalcogenide glass-based memory elements  
The present invention provides a design for a PCRAM element which incorporates multiple metal-containing germanium-selenide glass layers of diverse stoichiometries. The present invention also...
6949435 Asymmetric-area memory cell  
An asymmetric-area memory cell, and a fabrication method for forming an asymmetric-area memory cell, are provided. The method includes: forming a bottom electrode having an area; forming a CMR...
6949440 Method of forming a varactor  
A method of forming a varactor includes forming an ion well of a first conductivity type on a substrate and a plurality of isolation structures on the ion well. The isolation structures define at...
6946336 Method of making a nanoscale electronic device  
The present invention relates to a method of making a nanoscale electronic device wherein said device comprises a gap between about 0.1 nm and about 100 nm between at least two conductors,...
6943041 Magnetoresistive element and method for producing the same, as well as magnetic head, magnetic memory and magnetic recording device using the same  
The present invention provides a method for producing a magnetoresistive element including a tunnel insulating layer, and a first magnetic layer and a second magnetic layer that are laminated so as...
6943079 Semiconductor devices and methods for manufacturing the same  
Certain embodiments of the present invention relate to a method for manufacturing a semiconductor device, in which, when a cell capacitor of a DRAM and a capacitor element in an analog element...
6943099 Method for manufacturing gate structure with sides of its metal layer partially removed  
A method for manufacturing a gate structure has the steps of providing a substrate; forming a conducting layer on the substrate; forming a metal layer on the conducting layer; forming a patterned...
6943078 Method and structure for reducing leakage current in capacitors  
A method of forming a capacitor with reduced leakage current on a substrate in a semiconductor device is set forth. A first layer of a conductive material is formed over the substrate, and a second...
6939723 Method of forming haze-free BST films  
Described herein is a method for producing a haze-free (Ba, Sr)TiO 3 (BST) film, and devices incorporating the same. In one embodiment, the BST film is made haze-free by depositing the film with a...
6939758 Gate length control for semiconductor chip design  
A semiconductor device includes first and second polysilicon areas on a chip. The first polysilicon area corresponds to circuit elements of the semiconductor device. At least some of the first...
6936520 Method for fabricating semiconductor device having gate electrode together with resistance element  
A method for fabricating a semiconductor device comprises the steps of forming a polysilicon film 32 on a silicon substrate 10 , implanting a dopant into a region of the polysilicon film 32 ...
6936478 Ferroelectric capacitor with dielectric lining, semiconductor memory device employing same, and fabrication methods thereof  
A ferroelectric capacitor has a top electrode, a bottom electrode, a ferroelectric body disposed between the top and bottom electrodes, and a dielectric lining disposed below the top electrode and...
6933523 Semiconductor alignment aid  
An alignment aid for semiconductor devices. The alignment aid includes an area having a high level of reflectivity and an adjacent area having a of low level of reflectivity. The area having a low...
6929996 Corner rounding process for partial vertical transistor  
A double corner rounding process for a partial vertical cell. A first corner rounding process is performed after etching the substrate to form a shallow trench for device isolation. A second corner...
6927073 Methods of fabricating magnetoresistive memory devices  
In accordance with one or more embodiments of the present invention, a technique fabricating a magnetoresistive memory device, where the magnetoresistive memory device has a magnetic memory element...
6919212 Method for fabricating ferroelectric random access memory device with merged-top electrode-plateline capacitor  
The present invention relates to a method for fabricating a ferroelectric random access memory (FeRAM) device. The method includes the steps of: forming a first inter-layer insulation layer on a...
6919240 Flat aluminum electrolytic capacitor and method of manufacturing the same  
The present invention relates to a method of manufacturing a flat aluminum electrolytic capacitor comprising a separator impregnated with an electrolytic solution, an anode foil and a cathode foil,...
6916668 Methods for providing a magnetic shield for an integrated circuit having magnetoresistive memory cells  
A shielding arrangement for protecting a circuit containing magnetically sensitive materials from external stray magnetic fields. A shield of a material having a relatively high permeability is...
6916669 Self-aligned magnetic clad write line and its method of formation  
A self-aligned magnetic clad bit line structure ( 274 ) for a magnetic memory element ( 240 a ) and its method of formation are disclosed, wherein the self-aligned magnetic clad bit line structure...
6913964 Method of fabricating a one transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region  
A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell is provided that includes a field-effect transistor fabricated using a process compatible with a standard CMOS...
6911360 Fuse and method for forming  
An active fuse includes an active fuse geometry ( 120 ) that is used to form both a variable resistor ( 106 ) and a select transistor ( 110 ). In one embodiment, the active fuse geometry is formed...
6908808 Method of forming and storing data in a multiple state memory cell  
A method for forming a multiple state memory cell is provided. The method including forming a first electrode layer from a first conductive material, forming a second electrode layer from a second...
6906908 Semiconductor device and method of manufacturing the same  
Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate, an insulation region which covers the capacitor and has a first...
6905889 Inductor device with patterned ground shield and ribbing  
Inducting devices having a patterned ground shield with ribbing in an integrated circuit. In one embodiment, an inducting device comprises conductive turns to conduct current, a shield layer and a...
6900088 Semiconductor device and its manufacture method  
First and second gate electrodes are formed on first and second regions of a semiconductor substrate. Second conductivity type impurities are implanted into the second region to form first impurity...
6900094 Method of selective removal of SiGe alloys  
A method is disclosed of forming buried channel devices and surface channel devices on a heterostructure semiconductor substrate. In an embodiment, the method includes the steps of providing a...
6890768 Method of making layered superlattice material with ultra-thin top layer  
In the manufacture of an integrated circuit memory cell, a strontium bismuth tantalate or strontium bismuth tantalum niobate thin film layer ( 50 ) is deposited on a substrate ( 28, 49 ) and a...
6875652 Method for producing ferroelectric capacitors and integrated semiconductor memory chips  
The invention relates to a method for producing ferroelectric capacitors that are structured using the stack principle and that are used in integrated semiconductor memory chips. The individual...
6872579 Thin-film coil and method of forming same  
A method of forming a patterned thin film comprises the steps of forming a first plating layer and a second plating layer. Each of the steps of forming the plating layers includes: the step of...
6869872 Method of manufacturing a semiconductor memory device having a metal contact structure  
The present invention discloses a semiconductor memory device having a bit line and a metal contact stud, wherein the metal contact stud is formed on a different layer from a layer on which the bit...
6869840 Compensated-well electrostatic discharge protection devices  
Electrostatic discharge (ESD) protection structures utilizing bipolar conduction are disclosed. The structures each include a parasitic p-n-p bipolar transistor ( 102 ); some of the disclosed...
6869839 Method of fabricating a semiconductor device having an L-shaped spacer  
A method of fabricating a semiconductor device having an L-shaped spacer comprises forming a gate pattern on a transistor region of a semiconductor substrate. A disposable spacer is formed on an...
6869856 Process for manufacturing a semiconductor wafer integrating electronic devices including a structure for electromagnetic decoupling  
A process for manufacturing a semiconductor wafer integrating electronic devices and a structure for electromagnetic decoupling are disclosed. The method includes providing a wafer of semiconductor...
6867053 Fabrication of a FeRAM capacitor using a noble metal hardmask  
A ferroelectric capacitor is fabricated using a noble metal hardmask. A hardmask is deposited on a top electrode of a capacitor stack comprising a ferroelectric layer sandwiched between the top...
6858489 Semiconductor device manufacturing method  
This invention is directed to the reduction of voltage dependence and thus allows easy design of integrated semiconductor circuits. The device is equipped with a P− type resistance layer, in...
6858482 Method of manufacture of programmable switching circuits and memory cells employing a glass layer  
Programmable conductor memory cells in a stud configuration are fabricated in an integrated circuit by blanket deposition of layers. The layers include a bottom electrode in contact with a...
6858481 Memory device with active and passive layers  
A memory including memory cells having active and passive layers may store multiple information bits. The active layer may include an organic polymer that has a variable resistance based on the...
6856031 SRAM cell with well contacts and P+ diffusion crossing to ground or N+ diffusion crossing to VDD  
A low cost SRAM (Static Random Access Memory) cell is disclosed with P well and N well contacts and preferably with a P+ diffusion crossing to ground. The SRAM cell is complete at the M2 metal...
6855565 Semiconductor device having ferroelectric film and manufacturing method thereof  
First and second semiconductor regions are formed separately from each other in a semiconductor substrate. A gate electrode is formed above the semiconductor substrate which lies between the first...
6852549 Ferroelectric thin film processing for ferroelectric field-effect transistor  
The present invention relates to a method for manufacturing a ferroelectric field-effect transistor, particularly to a ferroelectric field-effect transistor with a...
Matches 301 - 350 out of 1043 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >