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6180445 |
Method to fabricate high Q inductor by redistribution layer when flip-chip package is employed
A new method is provided for the creation of a high Q inductor that can be applied together with the mounting of flip chip semiconductor die on a substrate. The process of the invention starts with...
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6180448 |
Semiconductor memory device having a capacitor over bitline structure and method for manufacturing the same
A semiconductor memory device having an improved step profile between a cell array region and peripheral circuit region, and a method for manufacturing the same, are provided. The semiconductor...
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6177300 |
Memory with storage cells having SOI drive and access transistors with tied floating body connections
An integrated circuit (10). The integrated circuit comprises a first SOI transistor (AT3) having a body and for performing first function. The integrated circuit further comprises a second SOI...
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6175137 |
Monolithic resistor having dynamically controllable impedance and method of manufacturing the same
A variable resistor, a method of manufacturing the same and a voltage bias circuit that incorporates at least one variable resistor. In one embodiment, the variable resistor includes: (1) a...
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6174763 |
Three-dimensional SRAM trench structure and fabrication method therefor
A three-dimensional five transistor SRAM trench structure and fabrication method therefor are set forth. The SRAM trench structure includes four field-effect transistors ("FETs") buried within a...
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6171902 |
Method of forming a DRAM cylinder shaped capacitor
A semiconductor device and a manufacturing method for a hyperfine structure wherein contact of a gate electrode with a side-wall composed of a silicon nitride layer within a contact hole due to an...
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6171904 |
Method for forming rugged polysilicon capacitor
The present invention relates to a method for forming rugged polysilicon capacitance electrodes uses for dynamic random access memory processes is disclosed. The method is capable in reducing...
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6169010 |
Method for making integrated circuit capacitor including anchored plug
A method for making an integrated circuit capacitor includes forming an interconnection line adjacent a substrate, forming a first dielectric layer on the interconnection line, forming a first...
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6165830 |
Method to decrease capacitance depletion, for a DRAM capacitor, via selective deposition of a doped polysilicon layer on a selectively formed hemispherical grain silicon layer
A process for creating a DRAM capacitor structure, featuring a doped polysilicon layer, overlying a crown shaped storage node electrode, has been developed. The process features the use of an HSG...
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6165831 |
Method of fabricating a buried contact in a static random access memory
A method of fabricating a static random access memory. A substrate having a gate is provided. A source/drain region is formed in the substrate beside the gate. A metal silicide layer is formed on...
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6165829 |
Thin film transistor and fabrication method therefor
A thin film transistor and a fabrication method therefor, which thin transistor includes: a stepped substrate provided with a sidewall between upper portion and lower portions thereof; an active...
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6162670 |
Method of fabricating a data-storage capacitor for a dynamic random-access memory device
A method is provided for fabricating a data-storage capacitor for a DRAM device, which can help increase the capacitance of the resulted capacitor. By this method, a first insulating layer, a...
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6162677 |
Semiconductor device fabricating method
In a semiconductor device fabricating method for fabricating a semiconductor device having a high-density region in which transistors are arranged with a relatively high density, and a low-density...
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6162672 |
Method for forming integrated circuit memory devices with high and low dopant concentration regions of different diffusivities
An integrated circuit memory device includes a substrate divided into a cell array region, a core region, and a peripheral circuit region. A plurality of memory cells in the memory cell region each...
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6162671 |
Method of forming capacitors having high dielectric constant material
Disclosed is a method of forming storage cell capacitors for use in dynamic random access memories, which comprises, after sequentially depositing a reaction barrier layer and a platinum layer on...
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6159785 |
Semiconductor device and manufacturing method thereof
An amorphous silicon film is formed on an interlayer insulating film to cover an upper surface of the interlayer insulating film, and a side surface and a bottom surface of an opening formed at the...
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6159817 |
Multi-tap thin film inductor
A thin film spiral inductor is formed on a ceramic or other suitable substrate in a manner which facilitates adjustment of the inductive value of the inductor after its fabrication on the...
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6159786 |
Well-controlled CMP process for DRAM technology
A new method of maintaining good control of the dielectric thickness over a top capacitor plate during planarization by CMP by introducing a CMP stop layer under the topmost dielectric layer is...
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6156600 |
Method for fabricating capacitor in integrated circuit
A method for fabricating a capacitor in an integrated circuit, using tantalum oxide as the dielectric layer to obtain a higher capacitance. A barrier layer is formed between the polysilicon layer...
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6156599 |
Method of making a semiconductor device with capacitor
A semiconductor device comprising a semiconductor substrate and a capacitor formed on the semiconductor substrate, wherein the capacitor is formed of a multilayer comprising a first electrode...
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6156602 |
Self-aligned precise high sheet RHO register for mixed-signal application
A new method is provided for the creation of a resistive load in a semiconductor device whereby the semiconductor device further contains gate electrodes and a capacitor. Field isolation regions...
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6156601 |
Method of forming DRAM matrix of basic organizational units each with pair of capacitors with hexagon shaped planar portion
A dynamic random access memory (DRAM) organized as a matrix of basic organizational units each having a capacitor pair. Each capacitor pair has one of the first capacitors and one of the second...
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6153460 |
Method of fabricating semiconductor memory device
A method of fabricating a semiconductor memory device comprises the steps of: (a) forming an interlayer insulating film on a semiconductor substrate, opening a contact hole in said interlayer...
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6153458 |
Method of forming a portion of a memory cell
The invention may be incorporated into a method for forming a vertically oriented semiconductor device structure, and the semiconductor structure formed thereby, by forming a first transistor over...
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6153459 |
Method of fabricating dual gate structure of embedded DRAM
A method of fabricating a dual gate of embedded DRAM forms a conductive layer on a substrate having a memory cell region and a logic circuitry. A gate structure is then formed on the substrate of...
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6150228 |
Method of manufacturing an SRAM with increased resistance length
A silicon nitride layer on a ground wire is used for an etching stopping layer so as to form a trench, after which a high-resistance load element is formed so as to extend the length of the...
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6150208 |
DRAM capacitors made from silicon-germanium and electrode-limited conduction dielectric films
An exemplary implementation of the present invention includes a capacitor for a dynamic random access memory cell having a first plate; a second plate; and a dielectric layer interposed between...
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6150206 |
Methods of forming integrated circuit capacitors using trench isolation and planarization techniques
Methods of forming integrated circuit capacitors include the steps of forming a trench in a first electrically insulating layer and then forming a first electrically conductive layer on a sidewall...
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6146936 |
Integrated circuitry, methods of reducing alpha particle inflicted damage to SRAM cells, methods of forming integrated circuitry, and methods of forming SRAM cells
The present invention pertains to methods of forming integrated circuitry, methods of forming SRAM cells, and methods of reducing alpha particle inflicted damage to SRAM cells. Additionally, the...
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6143596 |
Planarization for interlayer dielectric
The method includes forming a first dielectric layer on a wafer having cell area and cell boundary. The first dielectric layer is etched to generate a plurality of holes. A polysilicon layer is...
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6143614 |
Monolithic inductor
The monolithic inductor (30) includes a substrate (38), a spiral metal trace (32) disposed insulatively above the substrate (38), where a parasitic capacitance (56) is generated between the spiral...
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6140188 |
Semiconductor device having load device with trench isolation region and fabrication thereof
A small-area, high-resistance load device is fabricated in the same area used for the shallow trench isolation region. In an example embodiment, the load device comprises a series resistor coupled...
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6140204 |
Process for producing a semiconductor device having hemispherical grains (HSG)
Ingredient gas is first supplied into a reacting section disposed in an apparatus for chemical vapor deposition. Subsequently, a silicon film is deposited on a wafer under a condition that...
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6136704 |
Method for forming porous platinum films
A method for forming a platinum film includes providing a substrate, sputtering a crystalline platinum oxide layer over at least a portion of the substrate, and reducing the crystalline platinum...
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6133085 |
Method for making a DRAM capacitor using a rotated photolithography mask
A method of forming a bottom storage node of a DRAM capacitor over a contact plug is disclosed. The method comprises the steps of: depositing an oxide layer over the contact plug; etching the oxide...
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6133055 |
Method of forming a test key architecture
A method of forming a test key architecture on a silicon wafer. The method includes forming trench isolation regions between a source region and a drain region. Thereafter, a plurality of active...
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6133083 |
Method to fabricate embedded DRAM
A method for fabricating an embedded DRAM. A substrate having a memory circuit region and a logic circuit region is provided. A first gate, a first source/drain region and a second source/drain...
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6133084 |
Method of fabricating static random access memory
A method of fabricating a static random access memory. A gate oxide layer is formed on a substrate having active regions of an access transistor and a drive transistor. A Polysilicon layer is...
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6133079 |
Method for reducing substrate capacitive coupling of a thin film inductor by reverse P/N junctions
A method for reducing the capacitive coupling of an inductor on an integrated circuit chip is described. The method forms the inductor over an accumulation of dielectric layers used elsewhere in...
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6130462 |
Vertical poly load device in 4T SRAM technology
A novel vertical poly load device in 4T SRAM and a method for fabricating the same are disclosed. The poly load structure is a vertical device formed on a buried contact. The poly load vertical...
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6130137 |
Method of forming a resistor and integrated circuitry having a resistor construction
A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings...
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6127217 |
Method of forming highly resistive interconnects
Provided is a high resistance value vertically-integrated semiconductor interconnect, and a process to make such highly resistive interconnects together with low resistive interconnects in a...
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6127221 |
In situ, one step, formation of selective hemispherical grain silicon layer, and a nitride-oxide dielectric capacitor layer, for a DRAM application
A process for creating a DRAM capacitor structure, comprised of a storage node electrode, featuring an HSG silicon layer, on the surface of the storage node electrode, used to increase capacitor...
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6127214 |
Contact gate structure and method
A semiconductor device (2) includes contact gate structures (28, 30) associated with contacts (82, 84) to source/drain regions (42, 44). Each contact (82, 84) includes a polysilicon layer (50)...
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6127216 |
Heavily-doped polysilicon/germanium thin film formed by laser annealing
An ultra-large scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs utilize gate structures with...
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6124163 |
Integrated chip multiplayer decoupling capacitors
A multilayer decoupling capacitor structure is disclosed, having a first decoupling capacitor with one electrode formed in a conductively doped silicon substrate and a second electrode made of...
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6124162 |
Method for manufacturing cylindrical lower electrode of DRAM capacitor
A method for forming the cylindrical lower electrode of a capacitor includes the steps of providing a semiconductor substrate, and then forming an insulation layer over the substrate. Next, a...
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6124161 |
Method for fabricating a hemispherical silicon grain layer
A method for forming a hemispherical silicon grain (HSG) layer on a polysilicon electrode is provided. The method is suitable for a substrate, which has a dielectric layer over the substrate with...
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6121104 |
Charge cancellation technique for integrated circuit resistors
An integrated circuit resistor (18) has a layout in which a first parasitic capacitance (26) exists between first portions of the resistor (18) and a first integrated circuit feature (34), and a...
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6121082 |
Method of fabricating DRAM with novel landing pad process
A method for fabricating landing pads for DRAM cells is disclosed. The method comprises following steps: At first, a substrate formed with isolation regions, periphery transistor region and a...
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