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6303423 Method for forming high performance system-on-chip using post passivation process  
The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a...
6300179 Gate device with access channel formed in discrete post and method  
A method for fabricating a gate device includes forming a discrete post on a substrate. The discrete post protrudes from a surrounding area of the substrate and includes an access channel for the...
6300213 Semiconductor processing methods of forming a storage node of a capacitor  
A semiconductor processing method of forming a contact pedestal includes, a) providing a node location to which electrical connection is to be made; b) providing insulating dielectric material over...
6300217 Method for fabricating a semiconductor device including a step for forming an amorphous silicon layer followed by a crystallization thereof  
A method for fabricating a semiconductor device includes the steps of depositing an amorphous silicon layer on a substrate, and forming an oxidation film on a surface of the amorphous silicon layer...
6300181 Process for manufacturing an electronic device including MOS transistors with salicided junctions and non-salicided resistors  
A manufacturing process that includes, in succession: depositing a gate oxide layer on a silicon substrate defining a transistor area and a resistor area; depositing a multicrystal silicon layer on...
6300180 Method for forming an integrated circuit having improved polysilicon resistor structures  
A metal oxide semiconductor static random access memory (SRAM) includes NMOS transistors and resistor structures implemented without multiple polysilicon layers. According to a first embodiment,...
6300185 Polyacrystalline silicon film formation method  
In a method of forming a polycrystalline silicon film, the polycrystalline silicon film is formed under film formation conditions of a film formation rate of 0.9r av to 1.1r av , where r av ...
6297524 Multilayer capacitor structure having an array of concentric ring-shaped plates for deep sub-micron CMOS  
A capacitor structure having a first and at least a second conductor level of electrically conductive concentric ring-shaped lines. The conductive lines of the first and at least second levels are...
6297083 Method of forming four transistor SRAM cell having a resistor  
A device structure and a method of forming the structure comprising a resistor in a via opening between adjacent levels of metallization of a conventional field effect transistor (FET) by using...
6297084 Method for fabricating semiconductor memory  
A method for fabricating a semiconductor memory, in which a resistive layer is formed of a material identical to a material of a cell plug layer at a time of formation of the cell plug layer. In...
6291294 Method for making a stack bottom storage node having reduced crystallization of amorphous polysilicon  
A method for manufacturing a bottom storage node of a stack capacitor on a substrate is disclosed. The method comprises the steps of: (1) forming a first dielectric layer onto said substrate; (2)...
6291286 Two-step strap implantation of making deep trench capacitors for DRAM cells  
A method of fabricating deep trench capacitors of high density Dynamic Random Access Memory (DRAM) cells is disclosed: first, providing a semiconductor substrate, and then forming a trench on the...
6291281 Method of fabricating protection structure  
A method of fabricating a protection device. A contact resistor, or a protection diode and a contact resistor are formed in a substrate. The protection diode and the contact resistor are...
6291279 Method for forming different types of MOS transistors on a semiconductor wafer  
A semiconductor wafer has a substrate, a first region in the substrate that is used for a logic circuit, and a second region in the substrate that is used for a memory cell. A first gate in the...
6287911 Semiconductor device with silicide layers and fabrication method thereof  
A semiconductor device is provided, which is capable of high-speed operation of MOSFETs in a device section while suppressing the current leakage of MOSFETs in another device section even if the...
6287909 Method of fabricating a static random access memory  
A method of fabricating a buried contact in a static random access memory. A gate oxide layer, a first conducting layer and a masking layer are formed sequentially on a substrate. A buried contact...
6287932 Inductor with magnetic material layers  
A spiral inductor fabricated above a semiconductor substrate provides a large inductance while occupying only a small surface area. Including a layer of magnetic material above and below the...
6284584 Method of masking for periphery salicidation of active regions  
An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors...
6279585 Etching method and method for manufacturing semiconductor device using the same  
In a method for manufacturing a semiconductor device, a barrier metal disposed on a metallic thin film for forming a thin film resistor is patterned by wet-etching. The wet-etching produces a...
6277694 Fabrication method for a metal oxide semiconductor having a double diffused drain  
A method for fabricating a metal oxide semiconductor having a double-diffused drain, which is applicable to the fabrication of an electrostatic discharge protection present fabrication method for a...
6277685 Method of forming a node contact hole on a semiconductor wafer  
The present invention provides a method of forming a node contact hole on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, a first dielectric layer positioned on the...
6274422 Method for manufacturing a semiconductor device  
A first conductive type well layer is formed on a surface of a first conductive type semiconductor substrate. A second conductive type impurity diffusion layer having the conductive type opposite...
6271072 Method of manufacturing a storage node having five polysilicon bars  
A method for forming a dynamic random access memory cell with an increased capacitance capacitor having a storage node with five polysilicon bars is achieved. A photoresist mask is formed overlying...
6271570 Trench-free buried contact  
A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited...
6271073 Method of forming transistors in a peripheral circuit of a semiconductor memory device  
A method of forming a transistor in a peripheral circuit of a random access memory device wherein a transistor gate, capacitor electrode or other component in the memory cell array is formed...
6268240 Static semiconductor memory device capable of enhancing access speed  
In a static memory cell including first and second drive MOS transistors, first and second MOS transfer transistors and first and second load elements, the drain of the first drive MOS transistor...
6268229 Integrated circuit devices and methods employing amorphous silicon carbide resistor materials  
Integrated circuits, including field emission devices, have a resistor element of amorphous Si x C 1 -x wherein 0<x<1, and wherein the Si x C 1 -x incorporates at least one impurity...
6268281 Method to form self-aligned contacts with polysilicon plugs  
An improved method to form self-aligned contacts with polysilicon plugs is described. A semiconductor substrate is provided. A silicon oxide layer overlying the semiconductor substrate is...
6268241 Method of forming a self-aligned silicide structure in integrated circuit fabrication  
A method for forming a self-aligned silicide (or called salicide) structure in IC fabrication is described. This method is characterized by the step of making the top surface of a polysilicon-based...
6265264 Method of doping and HSG surface of a capacitor electrode with PH3 under a low temperature/high pressure processing condition  
A method of fabricating a capacitor of a semiconductor device maximizes the imurity density of HSG formed at a surface of an electrode of the capacitor and thereby improves capacitance and...
6265260 Method for making an integrated circuit capacitor including tantalum pentoxide  
A method for making an integrated circuit capacitor which in one embodiment preferably comprises the steps of: forming, adjacent a semiconductor substrate, a first metal electrode comprising a...
6265302 Partially recessed shallow trench isolation method for fabricating borderless contacts  
An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench liner of silicon nitride. The silicon...
6261892 Intra-chip AC isolation of RF passive components  
A method of fabricating an integrated circuit having active components, conductors and isolation regions on a substrate is disclosed, including forming a portion of at least one of the isolation...
6261891 Method of forming a passivation layer of a DRAM  
The present invention provides a method of forming a passivation layer of a DRAM on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, and two adjacent gates positioned...
6261933 Process for building borderless bitline, wordline amd DRAM structure  
It is a feature of the present invention that a subminimum dimension wordline links approximately minimum dimensional individual gate segments with the bitline contact being borderless to the...
6261893 Method for forming a magnetic layer of magnetic random access memory  
The present invention relates to a method for forming a magnetic layer of magnetic random access memory. In short, the method comprises following steps: providing a substrate; forming metal...
6258652 Spiral-shaped inductor structure for monolithic microwave integrated circuits having air gaps in underlying pedestal  
An inductor structure having a single crystal body with a spiral shaped pedestal formed in one surface and a ground plane conductor disposed over an opposite surface of the body. A spiral shaped...
6258650 Method for manufacturing semiconductor memory device  
A semiconductor memory device includes a substrate, a first insulation layer formed on the substrate, a plurality of bit lines arranged on the first insulation layer, a second insulation layer...
6258651 Method for forming an embedded memory and a logic circuit on a single substrate  
A method for forming an integrated circuit device that incorporate both an array of memory cells and an array of logic circuits on a single chip or substrate is disclosed. The substrate has a...
6258673 Multiple thickness of gate oxide  
A method of forming an integrated circuit having four thicknesses of gate oxide in four sets of active areas by: oxidizing the silicon substrate to form an initial oxide having a thickness...
6258653 Silicon nitride barrier for capacitance maximization of tantalum oxide capacitor  
A method of making a capacitor on a conductive surface, preferably on a polysilicon surface includes contamination cleaning the surface with a high density plasma (HDP) of a first gaseous agent,...
6255160 Cell design and process for making dynamic random access memory (DRAM) having one or more Gigabits of memory cells  
A method and novel DRAM cell design are described for making DRAM devices with more than a Gigabit memory cells. After forming the FETs and polycide word lines with a cap oxide and sidewall...
6251719 Poly gate process that provides a novel solution to fix poly-2 residue under poly-1 oxide for charge coupled devices  
A new method is provided for the creation of poly gate electrodes. A layer of poly-1 is deposited over the surface of a layer of ONO, a layer of TEOS-1 is deposited over the layer of poly-1. The...
6245627 Method of fabricating a load resistor for an SRAM  
A method of fabricating a load resistor for an SRAM. A substrate has a polysilicon layer formed thereon through a buried contact process. An inter-layer dielectric layer is formed over the...
6245611 Process for manufacturing semiconductor integrated circuit device  
In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell,...
6242297 Semiconductor device having an improved interconnection and method for fabricating the same  
P + -type source/drain regions for load transistors and N + -type source/drain regions for driver transistors are connected by means of P + -type source/drain region outgoing lead and N + -type...
6242296 Method of fabricating embedded DRAM  
A method of fabricating an embedded DRAM. A word line and a gate are formed in a memory region and a logic circuitry region on the substrate. An etching stop layer is formed over the substrate and...
6239011 Method of self-aligned contact hole etching by fluorine-containing discharges  
The practice of forming self-aligned contacts (SACs) in MOSFETs using a silicon nitride gate sidewall and a silicon nitride gate cap has found wide acceptance, particularly in the manufacture of...
6238993 Polysilicon load for 4T SRAM operation at cold temperatures  
This invention relates to the fabrication of integrated circuit devices and more particularly to a method for reducing the otherwise excessive negative TCR of low doped polysilicon load resistors...
6238972 Method for increasing capacitance  
The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and then...
Matches 601 - 650 out of 1035 < 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 >