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Match Document Document Title
6380045 Method of forming asymmetric wells for DRAM cells  
A fabrication method for forming asymmetric wells of a DRAM cell, and more particularly to a fabrication method for producing a transistor that is capable of reducing body effect, gate-swing and...
6380024 Method of fabricating an SRAM cell featuring dual silicide gates and four buried contact regions  
A process of fabricating an SRAM cell, comprised with four NMOS devices, and two PMOS devices, featuring a dual gate polycide structure, traversing both NMOS and PMOS device regions, and featuring...
6380578 High-speed stacked capacitor in SOI structure  
Implemented are a semiconductor device comprising a trench type capacitor having such a structure that a soft error tolerance is excellent, a contact resistance between an electrode and a metal...
6380025 Method of encapsulating a photovoltaic module by an encapsulating material and the photovoltaic module  
In the present invention, a diaphragm for pressurizing and heating an encapsulating material is pre-heated to a predetermined temperature before laminating a lamination unit comprising a...
6376298 Layout method for scalable design of the aggressive RAM cells using a poly-cap mask  
A method for integrating salicide and self-aligned contact processes in the fabrication of integrated circuits by using a poly cap mask and a special layout technique is described. A pair of gate...
6372565 Method of manufacturing SRAM cell  
The present invention discloses a static random access memory cell having a reduced cell size and method of manufacturing the same. According to the invention, the SRAM cell includes: a word line...
6372639 Method for constructing interconnects for sub-micron semiconductor devices and the resulting semiconductor devices  
A workpiece and method are provided for forming N polysilicon interconnects coupled to N contact openings in a semiconductor device. The workpiece includes an active area and N potential contact...
6368908 Method of fabricating dynamic random access memory capacitor  
A method of fabricating a capacitor includes formation of a stacked layer formed by alternately forming conductive layers and isolation layers and then patterning these layers to form a stacked...
6365481 Isotropic resistor protect etch to aid in residue removal  
Various methods of fabricating a circuit structure, such as a gate electrode or a resistor are provided. In one aspect, a method of fabricating a circuit structure is provided that includes forming...
6365461 Method of manufacturing epitaxial wafer  
Methods are designed to manufacture an epitaxial wafer wherein the formation of defects in an epitaxial layer is sufficiently suppressed even if the epitaxial wafer is prepared from a silicon...
6362071 Method for forming a semiconductor device with an opening in a dielectric layer  
In accordance with one embodiment of the present invention, a method is disclosed for forming a semiconductor device having an isolation region ( 601 ). A dielectric layer ( 108 ) is deposited and...
6362525 Circuit structure including a passive element formed within a grid array substrate and method for making the same  
A circuit structure combines an integrated circuit with a passive circuit element formed within a grid-array substrate. Formation of the circuit structure includes forming a passive circuit element...
6362508 Triple layer pre-metal dielectric structure for CMOS memory devices  
A CMOS memory device includes source and drain regions diffused into a substrate, a polysilicon gate structure formed over a channel region located between the first and second diffusion regions,...
6358756 Self-aligned, magnetoresistive random-access memory (MRAM) structure utilizing a spacer containment scheme  
This invention pertains to a method of fabricating a MRAM structure and the resulting structure. The MRAM structure of the invention has the pinned layer recessed within a trench with the upper...
6358809 Method of modifying properties of deposited thin film material  
A method of modifying a layer of thin film composite material to achieve one or more desired properties for the thin film layer which cannot be achieved by heat treatment at all practical...
6358788 Method of fabricating a wordline in a memory array of a semiconductor device  
Metal nitride and metal oxynitride extrusions often form on metal silicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of...
6355515 Wiring structure of semiconductor device and method for manufacturing the same  
A wiring structure of a semiconductor device and a method for manufacturing the same are provided. The wiring structure according to the present invention includes a body formed of a conductive...
6352888 Method of fabricating SRAM cell having a field region  
A static random access memory (SRAM) cell includes first and second load devices, first and second access transistors, first and second drive transistors, and two bit lines. The SRAM includes a...
6352868 Method and apparatus for wafer level burn-in  
A built-in circuit for wafer level burn-in of a die. The burn-in circuit includes a main burn-in control circuit, a word line control circuit and a bit line control circuit. A number of internal...
6350707 Method of fabricating capacitor dielectric  
The present invention provides a method of fabricating capacitor dielectric layer. A bottom electrode covered by a native oxide layer on a chip is provided. The chip is disposed into a low pressure...
6348370 Method to fabricate a self aligned source resistor in embedded flash memory applications  
A method for fabricating a semiconductor resistor in embedded FLASH memory applications is described. In the method a gate array ( 9 ) is formed on a semiconductor substrate. Isolations regions (...
6348391 Monolithic inductor with guard rings  
An integrated circuit and method of fabrication are disclosed for achieving electrical isolation between a spiral inductor and an underlying silicon substrate using standard semiconductor...
6348388 Process for fabricating a uniform gate oxide of a vertical transistor  
A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench...
6344386 Method for fabricating semiconductor device including memory cell region and CMOS logic region  
A CMOS transistor and a memory cell transistor are formed without causing deterioration to reliability and performance. A step of covering a memory cell region with an HTO film and forming...
6338993 Method to fabricate embedded DRAM with salicide logic cell structure  
A method for forming salicide on the peripheral logic region of the embedded DRAM without using a salicide block mask layer to protect the memory cell region of the embedded DRAM and without oxide...
6338994 Semiconductor device and method of fabricating thereof  
A semiconductor device having a bottom electrode, a ferroelectric film, and a top electrode formed on a semiconductor substrate, wherein the angle of each of the main cross sectional sides of the...
6339024 Reinforced integrated circuits  
A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1.5...
6335237 Methods of forming capacitor and bitline structures  
The invention encompasses a method of forming bitlines. A substrate is provided, and comprises a plurality of spaced electrical nodes. A bitline layer is formed over at least some of the spaced...
6333219 Method for forming a polysilicon node in a semiconductor device  
A self-aligned contact hole is formed in a cell area of a semiconductor device, and then a polysilicon layer is formed on both the cell area and a peripheral circuit area. A first etch back process...
6331455 Power rectifier device and method of fabricating power rectifier devices  
A power rectifier having low on resistance, mass recovery times and low forward voltage drop. In a preferred embodiment, the present invention provides a power rectifier device employing a vertical...
6329235 Method of performing a pocket implantation on a MOS transistor of a memory cell of a DRAM  
This invention provides a method of performing a pocket implantation on a MOS transistor of a memory cell of a DRAM. The DRAM on a predetermined area of a semiconductor wafer comprises memory cells...
6329236 Method for fabricating resistive load static random access memory device  
A method for fabricating a resistive load static random access memory (SRAM) capable of providing a high resistive load without local resistance variation, includes a step of forming an isolated...
6326256 Method of producing a laser trimmable thin film resistor in an integrated circuit  
A thin film resistor processing flow solves the problem of accurately incorporating the resistor (80) to be trimmed in an optimized multilayer stack (60,70). This is achieved by measuring the total...
6326257 Method of fabricating static random access memory with spacers  
A method of fabricating a static random access memory. A stacked gate is formed on a substrate. A lightly doped drain region and a lightly doped source region are formed in the substrate. A thin...
6323143 Method for making silicon nitride-oxide ultra-thin gate insulating layers for submicrometer field effect transistors  
A method for making an improved ultra-thin silicon nitride-oxide gate insulating layer for field effect transistors (FETs) is achieved. After forming a field oxide to electrically isolate device...
6323512 Nonvolatile ferroelectric capacitor and nonvolatile ferroelectric memory  
A nonvolatile ferroelectric capacitor comprising Bi 4 -x A x Ti 3 O 12 thin film which is obtained by substituting at least some atoms of nonvolatile element A such as La for volatile Bi atoms...
6323080 Conductive electrical contacts, capacitors, DRAMs, and integrated circuitry, and methods of forming conductive electrical contacts, capacitors, DRAMs, and integrated circuitry  
The invention encompasses DRAM constructions, capacitor constructions, conductive contacts, integrated circuitry, methods of forming DRAM constructions, and methods of forming capacitor...
6323127 Capacitor formed with Pt electrodes having a 3D cup-like shape with roughened inner and outer surfaces  
A noble metal electrode structure having a cup-like, approximately cylindrical shape, roughened inner and outer surfaces, and a surface area of at least 1 sq. micron or greater is provided as well...
6323079 Method for manufacturing a semiconductor device  
6319800 Static memory cell  
A static memory cell is described which has cross coupled pulldown transistors and dual access transistors. The memory cell is fabricated such that balanced current paths are formed through the two...
6316275 Method for fabricating a semiconductor component  
In a method for fabricating a semiconductor component, a first oxide layer is produced above a substrate. A capacitor is formed above the first oxide layer. The capacitor includes a bottom...
6313492 Integrated circuit chip produced by using frequency doubling hybrid photoresist  
A photoresist composition is disclosed having both negative tone and positive tone responses, giving rise to spaces being formed in the areas of diffraction which are exposed to intermediate...
6312983 Etching method for reducing bit line coupling in a DRAM  
A method for forming a bit line of a DRAM memory array is disclosed. The method comprises the steps of: forming an interlayer dielectric over the DRAM memory array; etching the interlayer...
6312982 Method of fabricating a trench capacitor  
This invention provides a semiconductor device by which a high-speed DRAM cell and logic circuit can be obtained without increasing the number of fabrication steps, and a method of fabricating the...
6309922 Method for fabrication of on-chip inductors and related structure  
Method for fabrication of on-chip inductors and related structure are disclosed. According to one embodiment, inductors are formed by patterning conductors within a certain dielectric layer in a...
6309930 SRAM cell arrangement and method for manufacturing same  
The SRAM cell arrangement comprises six MOS transistors per memory cell that are fashioned as vertical transistors. The MOS transistors are arranged at sidewalls of trenches (G1, G2, G4). Parts of...
6306703 Memory array having a digit line buried in an isolation region and method for forming same  
A memory array includes a semiconductor substrate, an isolation trench disposed in the substrate, and a conductor that is disposed in the trench. The array also includes a memory cell that is...
6306718 Method of making polysilicon resistor having adjustable temperature coefficients  
A polysilicon resistor is formed using a late implant process. Low dopant concentrations on the order of 6×10 19 to 3.75×10 20 have shown good results. with a reduced post anneal temperature....
6306704 Nonvolatile ferroelectric memory  
A nonvolatile ferroelectric memory comprising a main memory cell blocks including first and second wordlines, a first cell transistor whose gate is connected to the first wordline and one electrode...
6303422 Semiconductor memory and manufacturing method thereof  
A semiconductor memory in which a layout margin at the contact hole between wiring layers of a SRAM does not need and the wiring capacity at bit lines is reduced and the high speed processing is...
Matches 551 - 600 out of 1035 < 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 >