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7611947 Method of manufacturing semiconductor device  
A method of manufacturing a semiconductor device of the present invention consists of forming a trench in a trench-type cell transistor region; forming a gate insulating film and a gate material...
7611943 Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation  
A process ( 200 ) for making integrated circuits with a gate, uses a doped precursor ( 124, 126 N and/or 126 P) on barrier material ( 118 ) on gate dielectric ( 116 ). The process ( 200 ) involves...
7595234 Fabricating method for a metal oxide semiconductor transistor  
A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the...
7592222 Method of fabricating flash memory device  
The present invention relates to a method of fabricating a flash memory device. According to a method of fabricating a flash memory device in accordance with an aspect of the present invention, a...
7582502 Method for manufacturing back side illumination image sensor  
Provided are methods for manufacturing a back side illumination image sensor. In one method, an ion implantation layer is formed in an entire region of a front side of a first substrate. A device...
7569457 Method of fabricating semiconductor device  
An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region ( 3 ), and one...
7563663 Method of manufacturing semiconductor device with offset sidewall structure  
A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and...
7550357 Semiconductor device and fabricating method thereof  
A semiconductor device with a low drain current in the off-state of LDD type accommodating high voltages is provided. On the thermal oxide film, a polysilicon film and a CVD oxide film, and a...
7550351 Structure and method for creation of a transistor  
The invention is directed to an improved transistor that reduces dopant cross-diffusion and improves chip density. A first embodiment of the invention comprises gate electrode material partially...
7547592 PMOS depletable drain extension made from NMOS dual depletable drain extensions  
In accordance with an embodiment of the invention, there is an integrated circuit device having a complementary integrated circuit structure comprising a first MOS device. The first MOS device...
7544561 Electron mobility enhancement for MOS devices with nitrided polysilicon re-oxidation  
A semiconductor structure includes a PMOS device and an NMOS device. The PMOS device includes a first gate dielectric on a semiconductor substrate, a first gate electrode on the first gate...
7534677 Method of fabricating a dual gate oxide  
A method of fabricating a dual gate oxide of a semiconductor device includes forming a first gate insulation layer over an entire surface of a substrate, removing a portion of the first gate...
7504295 Methods for fabricating dynamic random access memory cells having laterally offset storage nodes  
DRAM cells include a common drain region in an integrated circuit substrate and first and second source regions in the integrated circuit substrate, a respective one of which is laterally offset...
7473595 Method for decreasing PN junction leakage current of dynamic random access memory  
A method for decreasing a PN junction leakage current of a dynamic random access memory (DRAM), including the steps of: preparing an NMOS transistor formed on a P-type silicon substrate and...
7465623 Methods for fabricating a semiconductor device on an SOI substrate  
Methods are provided for fabricating an SOI component on a semiconductor layer/insulator/substrate structure including a diode region formed in the substrate. The method comprises, in accordance...
7432144 Method for forming a transistor for reducing a channel length  
A method of forming a transistor including: forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate; forming a low energy ion implantation region aligned with...
7419867 CMOS gate structure comprising predoped semiconductor gate material with improved uniformity of dopant distribution and method of forming the structure  
By predoping of a layer of deposited semiconductor gate material by incorporating dopants during the deposition process, a high uniformity of the dopant distribution may be achieved in the gate...
7419863 Fabrication of semiconductor structure in which complementary field-effect transistors each have hypoabrupt body dopant distribution below at least one source/drain zone  
Complementary IGFETs ( 210 W and 220 W or 530 and 540 ) are fabricated so that the body dopant concentration in each IGFET decreases by at least 10 in moving from a subsurface location in the...
7399670 Methods of forming different gate structures in NMOS and PMOS regions and gate structures so formed  
A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors...
7396717 Method of forming a MOS transistor  
A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants...
7390719 Method of manufacturing a semiconductor device having a dual gate structure  
A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed...
7358131 Methods of forming SRAM constructions  
The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region...
7332389 Selective polysilicon stud growth  
A memory cell having a bit line contact is provided. The memory cell may be a 6F 2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole...
7285449 Semiconductor device manufacture method including process of implanting impurity into gate electrode independently from source /drain and semiconductor device manufactured by the method  
A gate electrode made of semiconductor is formed on the partial surface area of a semiconductor substrate. A mask member is formed on the surface of the semiconductor substrate in an area adjacent...
7282403 Temperature stable metal nitride gate electrode  
An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate...
7276407 Method for fabricating semiconductor device  
A method for fabricating a semiconductor device including on a single semiconductor substrate, a first MOS transistor having a first gate insulating film of a predetermined thickness, and second...
7265011 Method of manufacturing a transistor  
A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor...
7259054 Method of manufacturing a semiconductor device that includes a process for forming a high breakdown voltage field effect transistor  
With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n + type semiconductor regions,...
7253050 Transistor device and method of manufacture thereof  
Methods of forming CMOS devices and structures thereof. A workpiece is provided having a first region and a second region. A high k gate dielectric material is formed over the workpiece. A first...
7144767 NFETs using gate induced stress modulation  
A method for manufacturing an integrated circuit comprising a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor by covering the...
7132340 Application of post-pattern resist trim for reducing pocket-shadowing in SRAMs  
Methods ( 600, 700 ) are disclosed for minimizing the effect of pocket shadowing in the fabrication of an angled pocket implant ( 32 ) extending underlying a gate region ( 21 ) of a transistor ( 10...
7112480 Method and structure for a low voltage CMOS integrated circuit incorporating higher-voltage devices  
A CMOS integrated circuit ( 15 A-B-C) includes both relatively low-power ( 124, 126 ) and high-power ( 132, 134 ) CMOS transistors on the same chip. A 20V, relatively high-power PMOS device ( 134 )...
7098146 Semiconductor device having patterned SOI structure and method for fabricating the same  
A method for fabricating a semiconductor device, including forming a first insulation film, a first semiconductor layer, and a second insulation film in sequence in first to third regions of a...
7098099 Semiconductor device having optimized shallow junction geometries and method for fabrication thereof  
The present invention provides, in one embodiment, a method of fabricating a semiconductor device ( 100 ). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104,...
7078303 Method for manufacturing semiconductor device having thick insulating layer under gate side walls  
A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall...
7067370 Method of manufacturing a MOS transistor of a semiconductor device  
A method of manufacturing a transistor of a semiconductor device is provided. The method includes forming an N type gate pattern and a P type gate pattern on a substrate, implanting N type...
7064026 Semiconductor device having shared contact and fabrication method thereof  
Semiconductor devices and methods of fabrication. A device includes a semiconductor substrate, a gate electrode insulated from the semiconductor substrate by a gate insulation layer, LDD-type...
7063991 Methods of determining characteristics of doped regions on device wafers, and system for accomplishing same  
Disclosed herein are various methods of determining characteristics of doped regions on device wafers, and a system for accomplishing same. In one illustrative embodiment, the method includes...
7056798 Semiconductor device, method for manufacturing the same, and liquid jet apparatus  
A semiconductor device in which electro-thermal conversion elements and switching devices for flowing currents through the elements are integrated on a first conductive type semiconductor...
7045427 Polysilicon gate doping level variation for reduced leakage current  
A method for fabricating a transistor on a semiconductor substrate includes varying a polysilicon doping level near a first and second edge of a diffusion region with a polysilicon doping level of...
7045412 Field-effect type semiconductor device for power amplifier  
In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a...
7041549 Method for manufacturing semiconductor device  
In a method for manufacturing a semiconductor device, a gate insulating film and a gate electrode are first formed on a substrate. Next, Ge ions, Si ions, or the like are implanted to make the...
6953732 Method of manufacturing a semiconductor device including a mosfet with nitride sidewalls  
A method of manufacturing a semiconductor device includes providing a semiconductor substrate, and then forming a gate insulating layer on the semiconductor substrate. A lower gate electrode layer...
6933188 Use of a selective hard mask for the integration of double diffused drain MOS devices in deep sub-micron fabrication technologies  
A process for integrating the fabrication of double diffused drain (DDD) MOSFET devices with the fabrication sub-micron CMOS devices, has been developed. The process features formation of an...
6929995 Method of forming high voltage metal oxide semiconductor transistor  
A polysilicon layer and a first patterned photoresist layer are formed on a substrate. An ultraviolet curing process is performed to cure the first patterned photoresist layer. Then, a gate...
6924180 Method of forming a pocket implant region after formation of composite insulator spacers  
A process for forming a MOSFET device featuring a pocket region placed adjacent to only a top portion of the sides of a heavily doped source/drain region, has been developed. The process features...
6913979 Method of manufacturing a metal oxide semiconductor transistor  
Disclosed is a method of manufacturing a MOS transistor having an enhanced reliability. A passivation layer is formed on a gate electrode and on a substrate to prevent a generation of a recess on...
6908800 Tunable sidewall spacer process for CMOS integrated circuits  
A mixed voltage CMOS process for high reliability and high performance core transistors and input-output transistors with reduced mask steps. A gate stack ( 30 ) is formed over the silicon...
6894356 SRAM system having very lightly doped SRAM load transistors for improving SRAM cell stability and method for making the same  
A static random access memory (SRAM) cell is given increased stability and latch-up immunity by fabricating the PMOS load transistors of the SRAM cell to have a very low drain/source dopant...
6884672 Method for forming an electronic device  
Under the present invention, a layer of amorphous silicon is formed over a layer of gate dielectric. Over the layer of amorphous silicon, a gate cap dielectric is formed. The layer of amorphous...
Matches 1 - 50 out of 309 1 2 3 4 5 6 7 >