Patents in Class 438/228

Matches 1 - 50 out of 256

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Match	Document	Document Title
1	7605034	Integrated circuit memory cells and methods of forming An integrated circuit memory cell includes a combined first capacitor electrode and first transistor source/drain, a second capacitor electrode, a capacitor dielectric between the first and second...
2	7588978	Method for forming semiconductor device Embodiments relate to a method for forming a semiconductor device in which a first oxide layer may be deposited over a surface of a semiconductor substrate including high-voltage (HV) and...
3	7582522	Method and device for CMOS image sensing with separate source formation A method and device for image sensing. The method includes forming a first well and a second well in a substrate, forming a gate oxide layer on the substrate, and depositing a first gate region and...
4	7521312	Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers...
5	7507596	Method of fabricating a high quantum efficiency photodiode The present invention is CMOS image sensor and its method of fabrication. This invention provides an efficient structure to improve the quantum efficiency of a CMOS image sensor with borderless...
6	7445983	Method of manufacturing a semiconductor integrated circuit device A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor...
7	7410855	Semiconductor device A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode...
8	7371630	Patterned backside stress engineering for transistor performance optimization Some embodiments of the present invention include selectively inducing back side stress opposite transistor regions to optimize transistor performance.
9	7368354	Planar substrate devices integrated with FinFETs and method of manufacture A planar substrate device integrated with fin field effect transistors (FinFETs) and a method of manufacture comprises a silicon-on-insulator (SOI) wafer comprising a substrate; a buried insulator...
10	7335546	Method and device for CMOS image sensing with separate source formation A method and device for image sensing. The method includes forming a first well and a second well in a substrate, forming a gate oxide layer on the substrate, and depositing a first gate region and...
11	7323367	Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.
12	7279399	Method of forming isolated pocket in a semiconductor substrate A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms...
13	7273776	Methods of forming a P-well in an integrated circuit device The present invention is generally directed to a method of forming a p-well in an integrated circuit device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial...
14	7247534	Silicon device on Si:C-OI and SGOI and method of manufacture A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a...
15	7226834	PMD liner nitride films and fabrication methods for improved NMOS performance Semiconductor devices ( 102 ) and fabrication methods ( 10 ) are provided, in which a nitride film ( 130 ) is formed over NMOS transistors to impart a tensile stress in all or a portion of the NMOS...
16	7226832	Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS...
17	7211481	Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion,...
18	7145187	Substrate independent multiple input bi-directional ESD protection structure In a multiple input ESD protection structure, the inputs are isolated from the substrate by highly doped regions of opposite polarity to the input regions. Dual polarity is achieved by providing a...
19	7144796	Method of fabricating semiconductor components through implantation and diffusion in a semiconductor substrate A semiconductor element such as a DMOS-transistor is fabricated in a semiconductor substrate. Wells of opposite conductivity are formed by implanting and then thermally diffusing respective well...
20	7138311	Semiconductor integrated circuit device and manufacture method therefore A submicron CMOS transistor is mounted on the same substrate together with an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion...
21	7132323	CMOS well structure and method of forming the same A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a...
22	7112480	Method and structure for a low voltage CMOS integrated circuit incorporating higher-voltage devices A CMOS integrated circuit ( 15 A-B-C) includes both relatively low-power ( 124, 126 ) and high-power ( 132, 134 ) CMOS transistors on the same chip. A 20V, relatively high-power PMOS device ( 134 )...
23	7049699	Low RC structures for routing body-bias voltage Low RC structures for routing body-bias voltage are provided and described. These low RC structures are comprised of a deep well structure coupled to a metal structure.
24	7022566	Integrated radio frequency circuits An RF circuit may be formed over a triple well that creates two reverse biased junctions. By adjusting the bias across the junctions, the capacitance across the junctions can be reduced, reducing...
25	7008836	Method to provide a triple well in an epitaxially based CMOS or BiCMOS process A method to provide a triple well in an epitaxially based CMOS or B:CMOS process comprises the step of implanting the triple well prior to the epitaxial deposition.
26	7005354	Depletion drain-extended MOS transistors and methods for making the same Depletion drain-extended MOS transistor devices and fabrication methods for making the same are provided, in which a compensated channel region is provided with p and n type dopants to facilitate...
27	6995055	Structure of a semiconductor integrated circuit and method of manufacturing the same A method of fabricating CMOS transistors of first and second conductivity types in an SOI substrate includes the steps of etching contact holes and alignment marks through the semiconductor and...
28	6927116	Semiconductor device having a double-well structure and method for manufacturing the same A first well of the same conductivity type as that of a semiconductor substrate and a second well of a conductivity type opposite to that of the semiconductor substrate, are formed in the...
29	6908859	Low leakage power transistor and method of forming A transistor is formed in a semiconductor substrate. A deep n-well region is used in conjunction with a shallow n-well region. A lightly doped drain extension region is disposed between a drain...
30	6900091	Isolated complementary MOS devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the...
31	6900081	Method of manufacturing semiconductor integrated circuit device A semiconductor device has a depletion type MIS transistor, a transistor forming a masked ROM, and a submicron CMOS integrated on a single or common semiconductor substrate, while minimizing the...
32	6881634	Buried-channel transistor with reduced leakage current In one embodiment, a buried-channel transistor is fabricated by masking a portion of an active region adjacent to a trench and implanting a dopant in an exposed portion of the active region to...
33	6875650	Eliminating substrate noise by an electrically isolated high-voltage I/O transistor On the surface of a semiconductor material of a first conductivity type 101 a , a lateral MOS transistor 100 is described surrounded by a well 171 of the opposite conductivity type and, nested...
34	6853037	Fabrication of low power CMOS device with high reliability A semiconductor device includes a relatively lower threshold level MOSFET and relatively higher threshold level MOSFETs of n- and p-types. The higher threshold level MOSFETs have gate oxide films...
35	6841430	Semiconductor and fabrication method thereof A semiconductor device with p-channel and n-channel field effect devices formed on a common substrate, where the drain and source regions of the n-channel field effect device are formed within a...
36	6838328	Back-biased MOS device fabrication method A plurality of p-wells and n-wells are formed in a front side of a bulk material, and a plurality of n layers and p layers are alternately formed within the bulk material between a back side of the...
37	6806160	Method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process A method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process is provided. In the present lateral SCR device, the shallow trench isolation among the...
38	6806133	Method for fabricating semiconductor device with triple well structure A method for fabricating a triple well in a semiconductor device, includes the steps of forming a first well of a first conductive type with a first concentration lower than a first target...
39	6787410	Semiconductor device having dynamic threshold transistors and element isolation region and fabrication method thereof A semiconductor device with dynamic threshold transistors includes a complex element isolation region composed of a shallow element isolation region made of shallow trench isolation and deep...
40	6707115	Transistor with minimal hot electron injection A device comprising: a layer of gate oxide on a surface of the semiconductor substrate; a gate electrode formed on the surface of the gate oxide, the gate electrode having a drain side; a p-well...
41	6699740	Method for manufacturing a lateral double-diffused MOS transistor having stable characteristics and equal drift length A semiconductor device including a P-type semiconductor layer; an N-type first well on the surface of the semiconductor layer; a P-type second well on the surface of the first well; an N-type...
42	6667205	Method of forming retrograde n-well and p-well A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out...
43	6645854	Formation of a vertical junction throuph process simulation based optimization of implant doses and energies A substantially vertical isolation junction between semiconductor devices is provided. The substantially vertical junction between a P-doped region and an N-doped region allows the P-doped region...
44	6610581	Method of forming isolation film in semiconductor device There is disclosed a method of forming an isolation film in a semiconductor device, the method including the steps of: forming a silicon oxide film and a silicon nitride film in that order on a...
45	6589834	Semiconductor chip that isolates DRAM cells from the peripheral circuitry and reduces the cell leakage current The dynamic random access memory (DRAM) cells in a semiconductor chip are isolated from the peripheral circuitry by forming the DRAM cells directly in the substrate while the peripheral and other...
46	6583044	Buried channel in a substrate and method of making same A buried channel and a method of fabricating a buried channel in a substrate including depositing a layer of masking material onto a surface of a substrate, etching a groove in the masking layer,...
47	6569713	Method of fabricating read only memory A method of fabricating a read only memory. After forming bit lines and word lines in a substrate, a coding process is performed. A photoresist layer is formed on the substrate while performing the...
48	6521515	Deeply doped source/drains for reduction of silicide/silicon interface roughness Metal silicides form low resistance contacts on semiconductor devices such as transistors. Rough interfaces are formed between metal silicide contacts, such as NiSi and the source/drain regions of...
49	6518154	Method of forming semiconductor devices with differently composed metal-based gate electrodes MOS transistors and CMOS devices comprising a plurality of transistors including metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket...
50	6503787	Device and method for forming semiconductor interconnections in an integrated circuit substrate The present invention provides a semiconductor device, formed on a semiconductor wafer, comprising a tub, first and second active areas, and an interconnect. In one aspect of the present invention,...

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