Matches 201 - 250 out of 256 < 1 2 3 4 5 6 >
Match Document Document Title
5283200 Method of fabricating complementary semiconductor device  
According to this invention, an impurity for forming a P-well region and an impurity for forming an N-channel stopper are sequentially doped in an N-channel region, and an impurity for forming an...
5272097 Method for fabricating diodes for electrostatic discharge protection and voltage references  
A novel process is taught for forming diodes simultaneously with the formation of typical prior art LDD MOS devices. The diodes thus formed have low breakdown voltages, making them suitable for use...
5254487 Method of manufacturing high and low voltage CMOS transistors on a single chip  
A semiconductor device where high voltage CMOS transistors and low voltage CMOS transistors are installed on a single chip, is manufactured by a silicon gate CMOS process. In order to reduce the...
5252510 Method for manufacturing a CMOS device having twin wells and an alignment key region  
A method for manufacturing a CMOS semiconductor device having twin wells is disclosed. The method of manufacturing the CMOS device comprises the following. A silicon substrate is provided. A thick...
5219783 Method of making semiconductor well structure  
A method of forming doped well regions in a semiconductor layer 14 is disclosed herein. At least one n-doped region 30 and at least one p-doped region 36 are formed in the semiconductor layer 14....
5190888 Method for producing a doped polycide layer on a semiconductor substrate  
Method for producing a doped polycide layer on a semiconductor substrate. A polycide layer (14) is formed by producing a metal silicide layer (13a) on a polysilicon layer (12a). After the formation...
5141882 Semiconductor field effect device having channel stop and channel region formed in a well and manufacturing method therefor  
A method of forming a well on a semiconductor substrate and a transistor on the main surface of this well. A mask exposing a region for the well is formed on the main surface of the semiconductor...
5141890 CMOS sidewall oxide-lightly doped drain process  
A CMOS process wherein lightly doped drain extensions are fabricated in the N-channel devices without any additional masking steps. The present invention requires a specific sequence of steps,...
5134085 Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories  
This invention constitutes a 10-12 mask, split-polysilicon process for fabricating dynamic random access memories of the stacked capacitor type for the one-megabit generation and beyond. The...
5132241 Method of manufacturing minimum counterdoping in twin well process  
An improved method for manufacturing high density CMOS integrated circuits which minimizes counterdoping of the N and P well structures includes providing a composite masking layer which has layers...
5114868 Manufacturing method of well region in coms intergrated circuit  
First, N-type channel stoppers are formed in an element formation region of a P-channel MOS transistor and in an element isolation region of the P-channel MOS transistor, of a CMOS transistor....
5091324 Process for producing optimum intrinsic, long channel, and short channel MOS devices in VLSI structures  
Highly doped short channel NMOS devices with punch-through protection; intrinsic NMOS devices with low threshold voltage; and long channel NMOS and PMOS devices with low body factor; are...
5091332 Semiconductor field oxidation process  
Front end processing for a CMOS substrate resulting in the formation of n-wells, p-wells, channel stops and field oxide regions. Both the n-type and p-type dopant are implanted through silicon...
5071777 Method of fabricating implanted wells and islands of CMOS circuits  
A method is disclosed for forming implanted wells and islands of CMOS integrated circuits with a retrograde profile, i.e., with wells and islands having a smaller penetration depth, shallower...
5047358 Process for forming high and low voltage CMOS transistors on a single integrated circuit chip  
A process for forming both low voltage CMOS transistors and high voltage CMOS transistors on a common integrated circuit chip uses a common implantation and drive-in step to form both the n-type...
5036019 Method of producing a complementary-type semiconductor device  
A method of producing a MIS transistor such as a MOS transistor has a P type and an N type channel transistors. P type and N type well regions are provided with the N type and the P type channel...
5021358 Semiconductor fabrication process using sacrificial oxidation to reduce tunnel formation during tungsten deposition  
A method of fabricating a CMOS-type structure entails forming a pair of conductive portions (68 and 70) on a pair of dielectric portions (72 and 74) lying on monocrystalline silicon (60). N-type...
5010032 Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects  
A process for making CMOS device wherein the N-channel devices have n+ gates, and the P-channel devices have p+ gates. A TiN local interconnect system is used to connect the two types of gates, as...
4968639 Process for manufacturing CMOS integrated devices with reduced gate lengths  
A process for manufacturing CMOS integrated devices with gate lengths of less than one micron and high supply voltage is described. In order to improve the resistance of CMOS devices to breakdown...
4956306 Method for forming complementary patterns in a semiconductor material while using a single masking step  
A semiconductor material is overlayed with sequentially stacked layers including a protective layer, an affinity layer having an affinity for a second implant blocking material comprising tungsten,...
4943536 Transistor isolation  
A BICMOS semiconductor device (20) and method for its fabrication is disclosed. Bipolar, PMOS, and NMOS transistors (22, 26, and 28) are isolated from one another by a P type channel stop (54)...
4929565 High/low doping profile for twin well process  
A process for forming n- and p-wells in a semiconductor substrate wherein each well has a shallow, highly-doped surface layer whose depth may be independently controlled. This high/low doping...
4908327 Counter-doped transistor  
P channel and N channel CMOS FETs (22, 24) and a process for their simultaneous fabrication with a minimal number of masking steps are disclosed. After formation of gates (30, 32) for both P...
4891326 Semiconductor device and a process for manufacturing the same  
A process for fabricating a semiconductor device having n-channel and p-channel MOSFET's. Each MOSFET has a pair of side walls that are simultaneously formed on both sides of the gate electrode....
4853340 Semiconductor device isolated by a pair of field oxide regions  
An integrated circuit semiconductor device having first and second circuit elements isolated by an improved isolation region is disclosed. The isolation region includes first and second thick...
4847213 Process for providing isolation between CMOS devices  
A process is disclosed for the selective oxidation of MOS devices which preferentially removes implanted field doping from selected silicon substrate regions. In one embodiment, a CMOS substrate is...
4771014 Process for manufacturing LDD CMOS devices  
A method for making a CMOS integrated circuit device saves on masking steps by using unmasked blanket implantations at various steps of the process, such as setting the threshold voltages of the...
4767721 Double layer photoresist process for well self-align and ion implantation masking  
A technique is disclosed for obtaining a self-aligned twin-well structure in a CMOS process. A double layer of two different photoresist materials is employed to obtain an overhang photoresist...
4761384 Forming retrograde twin wells by outdiffusion of impurity ions in epitaxial layer followed by CMOS device processing  
A method for the manufacture of LSI complementary MOS field effect transistor circuits to increase the latch-up hardness of the n-channel and p-channel field effect transistors while retaining good...
4743563 Process of controlling surface doping  
A process is disclosed for controlling the surface doping of two regions of a semiconductor device and more specifically for using such control to achieve the necessary field doping in a CMOS...
4731343 Method for manufacturing insulation separating the active regions of a VLSI CMOS circuit  
The invention relates to a method for the manufacture of insulating portions separating the active regions of a VLSI CMOS circuit wherein an oxide coated silicon substrate is etched in those...
4728619 Field implant process for CMOS using germanium  
A complementary metal-oxide-semiconductor (CMOS) isolation structure where the field isolation structure between the adjacent areas of different conductivity types has a channel stop doped with...
4717683 CMOS process  
A process is disclosed for fabricating complementary insulated gate field effect transistors including doped field isolation regions and optional punch through protection. In one embodiment of...
4710265 Method of producing semiconductor integrated circuit having parasitic channel stopper region  
A complementary MOS type integrated circuit is produced by a method which comprises the steps of: disposing a first mask material layer on the surface of a semiconductor substrate, the first mask...
4707455 Method of fabricating a twin tub CMOS device  
A method of fabricating a semiconductor device having a symmetric and complementary P-well and N-well. The novel method involves the introduction of a first dopant type into a semiconductor...
4697332 Method of making tri-well CMOS by self-aligned process  
A semiconductor structure having at least three types of wells which may be of different doping levels and methods of manufacturing such a structure, are disclosed. In one method, regions which...
4696092 Method of making field-plate isolated CMOS devices  
A dynamic read/write memory or the like is made by a twin-well CMOS process that employs field-plate isolation rather than thick field oxide, with no separate channel stop implant. The field plate...
4677739 High density CMOS integrated circuit manufacturing process  
A semiconductor device such as a dynamic read/write memory or the like is made by a twin-well CMOS process that employs a minimum number of photomasks. Field oxide isolation areas are formed in...
4626450 Process for producing semiconductor devices  
A process for producing semiconductor devices having excellent electric characteristics such as high threshold voltage Vth and small leakage current, maintaining high yields while preventing the...
4613885 High-voltage CMOS process  
A high-voltage CMOS process, providing (for 5 micron geometries) both field thresholds and junction breakdowns in excess of 20 volts, wherein only one channel stop implant is used. A double-well...
4590663 High voltage CMOS technology with N-channel source/drain extensions  
N-channel devices are fabricated with lightly doped drain/source extensions in a CMOS process, without the requirement of an extra mask level. A merged mask technique uses an oversized version of...
4584027 Twin well single mask CMOS process  
A twin-well process is formed using a single mask and lift-off techniques. The single implant mask is formed and the first well implanted followed by the deposition of a low temperature CVD film...
4566914 Method of forming localized epitaxy and devices formed therein  
An integrated circuit structure for isolating circuit structures in closely packed integrated circuits, and a method for making the same. The isolation structure includes a semiconductor body...
4558508 Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step  
A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells...
4554726 CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well  
To minimize the number of independent masking operations in the manufacture of a CMOS integrated circuit device using twin tub technology, the n-tub is made by separate phosphorus and arsenic...
4549340 Method of making CMOS semiconductor device using specially positioned, retained masks, and product formed thereby  
Disclosed is a method of manufacturing a semiconductor device which includes MOSFETs of the two-channel conductivity types of P- and N-channel types on a single semiconductor substrate. According...
4516316 Method of making improved twin wells for CMOS devices by controlling spatial separation  
An improved method for forming complementary wells in a substrate is disclosed. A polysilicon layer is applied to the substrate, and the polysilicon layer is doped. An oxidation barrier layer is...
4505027 Method of making MOS device using metal silicides or polysilicon for gates and impurity source for active regions  
The invention relates to a method for producing MOS transistors with flat source/drain zones, short channel lengths, and a self aligned contacting plane comprised of a metal silicide. In this...
4498223 Method of fabrication of monolithic integrated circuit structure  
A body of silicon has sectors of N-type and P-type covered by silicon oxide gate layers with adjacent regions covered by a thicker silicon oxide field layer. Gate members of N-type polycrystalline...
4459741 Method for producing VLSI complementary MOS field effect transistor circuits  
Analog or digital MOS circuits in VLSI technology are produced by a method in which the manufacture of two troughs (5, 8) occurs with only one mask (3) used in production of the p-trough (5). The...
Matches 201 - 250 out of 256 < 1 2 3 4 5 6 >