Patents in Class 438/227

Matches 1 - 50 out of 219

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Match	Document	Document Title
1	8124468	Process of forming an electronic device including a well region An electronic device including an integrated circuit can include a buried conductive region and a semiconductor layer overlying the buried conductive region, and a vertical conductive structure...
2	8076716	Electronic device including a trench and a conductive structure therein An electronic device can include a transistor. In an embodiment, the transistor can include a semiconductor layer having a primary surface and a conductive structure. The conductive structure can...
3	8071436	Method of fabricating a semiconductor device having a lateral double diffused MOSFET transistor with a lightly doped source and CMOS transistor Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with...
4	8049231	Quantum photonic imagers and methods of fabrication thereof Emissive quantum photonic imagers comprised of a spatial array of digitally addressable multicolor pixels. Each pixel is a vertical stack of multiple semiconductor laser diodes, each of which can...
5	7981739	Method of fabricating a lateral double-diffused MOSFET (LDMOS) transistor and a conventional CMOS transistor A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the...
6	7972917	Method for manufacturing semiconductor device and semiconductor device A method for manufacturing a semiconductor device is disclosed. The method includes: forming a LDMOS region, an offset drain MOS region, and a CMOS region; simultaneously forming a first well in...
7	7968393	Semiconductor device, design method and structure A semiconductor device can include at least a first diffusion region formed by doping a semiconductor substrate and at least a second diffusion region formed by doping the semiconductor substrate...
8	7902017	Process of forming an electronic device including a trench and a conductive structure therein A process of forming an electronic device can include providing a workpiece comprising a substrate, including an underlying doped region, and a semiconductor layer overlying the underlying doped...
9	7902020	Semiconductor device and method of manufacturing the same A semiconductor device includes a first conductivity-type deep well formed in a substrate, a plurality of device isolation layers formed in the substrate in which the first conductivity-type deep...
10	7868379	Electronic device including a trench and a conductive structure therein An electronic device can include a transistor. In an embodiment, the transistor can include a semiconductor layer having a primary surface and a conductive structure. The conductive structure can...
11	7813711	Stacking baseband circuits using deep n-well and increased supply voltage A method of designing stacked circuits for an integrated circuit is described. In this method, a plurality of devices that are stackable may be determined. Some of those devices, i.e. a subset of...
12	7754593	Semiconductor device and manufacturing method therefor A method of manufacturing a semiconductor device comprises forming a gate insulation film on a semiconductor substrate; forming a first gate electrode and a second gate electrode on the gate...
13	7709365	CMOS well structure and method of forming the same A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a...
14	7691700	Multi-stage implant to improve device characteristics One aspect of the inventors' concept relates to a method of forming a semiconductor device. In this method, a gate structure is formed over a semiconductor body. A source/drain mask is patterned...
15	7645664	Layout pattern for deep well region to facilitate routing body-bias voltage Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh...
16	7632732	Method of manufacturing MOS transistor A method of manufacturing a transistor may include: forming a first well over a silicon substrate; forming a first mask pattern over the silicon substrate and using the formed first mask pattern to...
17	7550344	Semiconductor device and method for fabricating the same A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper...
18	7482220	Semiconductor device having deep trench charge compensation regions and method In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the...
19	7482218	Low-capacitance input/output and electrostatic discharge circuit for protecting an integrated circuit from electrostatic discharge A transistor formed on a semiconductor substrate of a first conductivity type in a well formed in the substrate and doped with the first conductivity type to an impurity level higher than that of...
20	7364959	Method for manufacturing a MOS transistor A method for manufacturing a MOS transistor integrated into a chip of semi-conductive material comprising a first and a second active region which extend from the inside of the chip to a surface of...
21	7351627	Method of manufacturing semiconductor device using gate-through ion implantation Disclosed herein is a method of manufacturing a semiconductor device via gate-through ion implantation, comprising forming a gate stack on a semiconductor substrate and performing ion implantation...
22	7336530	CMOS pixel with dual gate PMOS A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N− well. The N− well is in a P− type substrate. The two P+ regions form the source and drain of a PMOS trans...
23	7247534	Silicon device on Si:C-OI and SGOI and method of manufacture A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a...
24	7163856	Method of fabricating a lateral double-diffused mosfet (LDMOS) transistor and a conventional CMOS transistor A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the...
25	7145187	Substrate independent multiple input bi-directional ESD protection structure In a multiple input ESD protection structure, the inputs are isolated from the substrate by highly doped regions of opposite polarity to the input regions. Dual polarity is achieved by providing a...
26	6984855	Manufacturing method of semiconductor device and semiconductor device A semiconductor device comprising a buried insulating film formed in a substrate; a protective film formed on the buried insulating film covering corresponding diffusion regions of a P-type MISFET...
27	6982196	Oxidation method for altering a film structure and CMOS transistor structure formed therewith A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a...
28	6977195	Test structure for characterizing junction leakage current For characterizing bulk leakage current of a junction, a center junction surrounded by an isolation structure is formed with a first depth. In addition, at least one periphery junction having a...
29	6929992	Strained silicon MOSFETs having NMOS gates with work functions for compensating NMOS threshold voltage shift The threshold voltage shift exhibited by strained silicon NMOS devices is compensated with respect to the threshold voltages of PMOS devices formed on the same substrate by increasing the work...
30	6921701	Method of manufacturing and structure of semiconductor device (DEMOS) with field oxide structure A method of forming a semiconductor device includes forming a body region of a semiconductor substrate and forming a drift region adjacent at least a portion of the body region. A dopant is used to...
31	6900101	LDMOS transistors and methods for making the same LDMOS transistor devices and fabrication methods are provided, in which additional dopants are provided to region of a substrate near a thick dielectric between the channel and the drain to reduce...
32	6897095	Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode A semiconductor fabrication process includes forming first and second transistors over first and second well regions, respectively where the first transistor has a first gate dielectric and the...
33	6887750	Method for manufacturing semiconductor device including implanting a first impurity through an anti-oxidation mask A method is provided for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor with different driving voltages provided in a common...
34	6853037	Fabrication of low power CMOS device with high reliability A semiconductor device includes a relatively lower threshold level MOSFET and relatively higher threshold level MOSFETs of n- and p-types. The higher threshold level MOSFETs have gate oxide films...
35	6852599	Method for fabricating MOS transistors A method for fabricating a metal oxide semiconductor (MOS) transistor, which can reduce the junction capacitance without degradation of transistor characteristics including forming a buffer oxide...
36	6841430	Semiconductor and fabrication method thereof A semiconductor device with p-channel and n-channel field effect devices formed on a common substrate, where the drain and source regions of the n-channel field effect device are formed within a...
37	6806160	Method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process A method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process is provided. In the present lateral SCR device, the shallow trench isolation among the...
38	6800513	Manufacturing semiconductor device including forming a buried gate covered by an insulative film and a channel layer A high performance super-minituarized double gate SOIMOS being fabricated by re-distributing the impurity with high concentration at the interface of a buried gate insulative film and by aligning...
39	6787410	Semiconductor device having dynamic threshold transistors and element isolation region and fabrication method thereof A semiconductor device with dynamic threshold transistors includes a complex element isolation region composed of a shallow element isolation region made of shallow trench isolation and deep...
40	6777280	Method for fabricating an integrated circuit with a transistor electrode Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to...
41	6767780	Method for fabricating CMOS transistor A method for fabricating a CMOS transistor is disclosed. The present invention provides a method for producing a CMOS transistor having enhanced performance since a short channel characteristic and...
42	6723593	Deep submicron MOS transistor with increased threshold voltage A deep submicron MOS transistor is formed with multiple control gates by forming side wall control gates adjacent to the gate oxide spacers over heavily-doped regions of the source and drain...
43	6720223	Power A method of manufacturing a power switching transistor for a fluid ejection device includes forming a diffused drain region and a diffused source region separated by a channel region. The diffused...
44	6713338	Method for fabricating source/drain devices A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed thereon, a first doped area is formed on a first side of the gate on the semiconductor...
45	6707115	Transistor with minimal hot electron injection A device comprising: a layer of gate oxide on a surface of the semiconductor substrate; a gate electrode formed on the surface of the gate oxide, the gate electrode having a drain side; a p-well...
46	6682965	Method of forming n-and p- channel field effect transistors on the same silicon layer having a strain effect A method for forming a Field Effect Transistor (FET) within a strain effect semiconductor layer is disclosed, whereby the source and drain of the FET are formed only in the strain effect silicon...
47	6667200	Method for forming transistor of semiconductor device A method for forming a transistor of a semiconductor device, including the step of forming channel layers of a first and a second conductive types, performing high temperature thermal process to...
48	6667205	Method of forming retrograde n-well and p-well A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out...
49	6630710	Elevated channel MOSFET The present invention provides a semiconductor device (e.g., MOSFET) having a channel above the surface of the wafer containing a well and a junction. The elevated channel may be selectively...
50	6613626	Method of forming CMOS transistor having a deep sub-micron mid-gap metal gate A CMOS transistor is formed on a single crystal silicon substrate. Active regions are formed on the substrate, including an nMOST active region and a pMOST active region. An epitaxial layer of...

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