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8173501 Reduced STI topography in high-K metal gate transistors by using a mask after channel semiconductor alloy deposition  
In a manufacturing strategy for providing high-k metal gate electrode structures in an early manufacturing stage, process-related non-uniformities during and after the patterning of the gate...
8138523 Semiconductor device having silicon on stressed liner (SOL)  
A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate...
8124470 Strained thin body semiconductor-on-insulator substrate and device  
A method of forming a strained, semiconductor-on-insulator substrate includes forming a second semiconductor layer on a first semiconductor substrate. The second semiconductor is lattice matched to...
8125031 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Low on-resistance lateral double-diffused MOS device  
A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and...
8119471 Semiconductor device and method for manufacturing the same  
A method for manufacturing a semiconductor device including a vertical double-diffusedmetal-oxide-semiconductor (VDMOS) transistor includes preparing a semiconductor substrate and injecting a first...
8114745 High voltage CMOS devices  
A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type...
8102030 Semiconductor device with strain  
A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active...
8101450 Photodetector isolation in image sensors  
Shallow trench isolation regions are disposed in an n-type silicon semiconductor layer laterally adjacent to a collection region of a photodetector and laterally adjacent to a charge-to-voltage...
8093111 Semiconductor device including partial silicon on insulator fin structure and method for fabricating the same  
A method for fabricating a semiconductor device comprises forming a partial-insulated substrate comprising an insulating region located below both a channel region of a cell transistor and one of a...
8092721 Deposition of ternary oxide films containing ruthenium and alkali earth metals  
Methods and compositions for the deposition of ternary oxide films containing ruthenium and an alkali earth metal.
8084318 Methods of fabricating integrated circuit devices including strained channel regions and related devices  
A method of fabricating an integrated circuit device includes forming first and second gate patterns on surfaces of a semiconductor substrate in PMOS and NMOS regions, respectively, of the...
8084317 Semiconductor device and method of manufacturing the same  
Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a gate electrode on a semiconductor substrate having a device isolation region, a...
8076725 Semiconductor device and method for manufacturing the same  
An impurity buried layer constructed by two buried regions formed by impurities of identical type exist, a buried region formed by an impurity having a slow diffusion speed is provided on the...
8067281 Method of fabricating complementary metal-oxide-semiconductor (CMOS) Device  
A method of fabricating a CMOS device is provided. First, first and second gates, first and second offset spacers and first and second lightly-doped regions are respectively formed in first and...
8067282 Method for selective formation of trench  
A method for selective formation of trenches is disclosed. First, a substrate is provided. The substrate includes a first semiconductor element and a second semiconductor element. The first...
8053309 Methods of fabricating semiconductor devices  
A semiconductor device includes a semiconductor substrate that includes first and second regions; first, second, and third insulating layers; a capacitor dielectric layer that includes first and...
8048752 Spacer shape engineering for void-free gap-filling process  
A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the...
8043930 Semiconductor memory device and method of manufacturing the same  
A semiconductor memory device includes first and second element isolation insulating films, first and second gate insulating films, first and second gate wiring and first and second mask layer....
8039340 Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate  
A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides...
8039335 Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain  
By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor...
8039339 Separate layer formation in a semiconductor device  
A semiconductor device is formed. A first gate dielectric layer is formed over the semiconductor layer. A first conductive layer is formed over the first gate dielectric. A first separation layer...
8017471 Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry  
A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI)...
8008146 Different thickness oxide silicon nanowire field effect transistors  
A method (that produces a structure) patterns at least two wires of semiconductor material such that a first wire of the wires has a larger perimeter than a second wire of the wires. The method...
7998811 Semiconductor device and method for semiconductor device  
A semiconductor device includes a semiconductor substrate, a memory cell region provided on the semiconductor substrate, a word line provided on the memory cell region, a first gate insulating film...
7998805 Component with sensitive component structures and method for the production thereof  
An electrical component has electrically conducting structures placed on an electrically isolating or semiconductive substrate and component structures sensitive to a voltage or an electrical...
7985655 Through-via and method of forming  
In one embodiment, a method of forming a via includes providing a semiconductor substrate, wherein the semiconductor substrate comprises a through-via region, forming isolation openings and a...
7981800 Shallow trench isolation structures and methods for forming the same  
A shallow trench isolation (STI) structure and method for forming the same is provided that reduces defects in a nitride film used as a field oxide mask and variations in pad oxide thickness....
7977198 Semiconductor device and method of manufacturing semiconductor device  
A semiconductor device is provided. The semiconductor device in which a field effect transistor utilizing a heterojunction is formed in a device formation region sectioned by a device separation...
7947551 Method of forming a shallow trench isolation structure  
An embodiment of the disclosure includes a method of forming a shallow trench isolation structure. A substrate is provided. The substrate includes a top surface. A trench is formed to extend from...
7947550 Method of forming semiconductor device  
A semiconductor device may include, but is not limited to, first and second well regions, and a well isolation region isolating the first and second well regions. The first and second well regions...
7944005 Semiconductor device and method for fabricating the same  
A semiconductor device includes a semiconductor substrate including an NMOS region and a PMOS region, active regions of the semiconductor substrate defined by a device isolation structure formed in...
7939422 Methods of thin film process  
A method for forming a semiconductor structure includes forming a plurality of features across a surface of a substrate, with at least one space being between two adjacent features. A first...
7939394 Multiple-depth STI trenches in integrated circuit fabrication  
Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause...
7932143 Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods  
Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device...
7919380 Method of manufacturing a transistor in semiconductor device having a gate electrode located between the trenches formed in low-concentration regions of the source and drain regions including high-concentration regions formed at the bottom of the trenches  
The present invention relates to a transistor in a semiconductor device and method of manufacturing the same. Trenches are formed in a semiconductor substrate at gate edges. Low-concentration...
7915138 Methods of manufacturing non-volatile memory devices  
In a method of manufacturing a non-volatile memory device, a conductive structure is formed on a substrate. The conductive structure includes a tunnel oxide pattern, a first conductive pattern, a...
7910453 Storage nitride encapsulation for non-planar sonos NAND flash charge retention  
The present disclosure provides a method of manufacturing a microelectronic device. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate,...
7906383 Stress transfer in an interlayer dielectric by providing a stressed dielectric layer above a stress-neutral dielectric material in a semiconductor device  
By forming a stressed dielectric layer on different transistors and subsequently relaxing a portion thereof, the overall process efficiency in an approach for creating strain in channel regions of...
7902609 Semiconductor devices including multiple stress films in interface area  
A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second...
7883955 Gate dielectric/isolation structure formation in high/low voltage regions of semiconductor device  
A semiconductor device has a thicker gate dielectric layer (gate-insulation film 16 of, e.g., 40 nm) for a high voltage PMOS transistor (Tr1) that is formed simultaneously in a first thermal...
7875512 Method for manufacturing semiconductor device  
According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method including: forming a first region and a second region in a...
7875514 Technique for compensating for a difference in deposition behavior in an interlayer dielectric material  
By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an...
7855407 CMOS image sensor and method for manufacturing the same  
Embodiments relate to a Complementary Metal Oxide Semiconductor (CMOS) image sensor, and to a method for manufacturing the same, that improves the low-light level characteristics of the CMOS image...
7851297 Dual workfunction semiconductor device  
A dual workfunction semiconductor device which comprises a first and second control electrode comprising a metal-semiconductor compound, e.g. a silicide or a germanide, and a dual workfunction...
7838945 Semiconductor device and manufacturing method thereof  
A semiconductor device includes first and second active regions on a semiconductor substrate, separated by an element isolation region; a line-shaped electrode disposed from over the first to over...
7838917 CMOS image sensor and method of fabricating the same  
A CMOS image sensor and method for fabricating the same, wherein the CMOS image sensor has minimized dark current at the boundary area between a photodiode and an isolation layer. The present...
7824977 Completely decoupled high voltage and low voltage transistor manufacturing processes  
A semiconductor wafer includes at least a partially manufactured high voltage transistor covered by a high-voltage low voltage decoupling layer and at least a partially manufactured low voltage...
7824976 Semiconductor apparatus and method of manufacturing the semiconductor apparatus  
A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an...
7811878 Method of manufacturing SOI substrate  
To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on...
7790561 Gate sidewall spacer and method of manufacture therefor  
The present invention provides a method for manufacturing a semiconductor device, a semiconductor device, and a method for manufacturing an integrated circuit including a semiconductor device. The...
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