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9006789 Compressive strained III-V complementary metal oxide semiconductor (CMOS) device  
A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on...
9000501 Semiconductor integrated circuit, electronic device, solid-state imaging apparatus, and imaging apparatus  
A semiconductor integrated circuit includes a first semiconductor substrate in which a part of an analog circuit is formed between the analog circuit and a digital circuit which subjects an analog...
8987081 Method of manufacturing semiconductor device with offset sidewall structure  
A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and...
8969969 High threshold voltage NMOS transistors for low power IC technology  
Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively...
8969149 Stacked semiconductor nanowires with tunnel spacers  
A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure...
8962417 Method and structure for pFET junction profile with SiGe channel  
A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the...
8962410 Transistors with different threshold voltages  
A first transistor and a second transistor are formed with different threshold voltages. A first gate is formed over the first region of a substrate for a first transistor and a second gate over...
8951857 Method for implanting ions in semiconductor device  
The present invention provides various methods for implanting ions in a semiconductor device that substantially compensate for a difference in threshold voltages between a central portion and edge...
8951866 Methods of fabricating semiconductor devices and semiconductor devices including threshold voltage control regions  
A semiconductor device includes a semiconductor substrate including isolation regions defining first and second active regions having a first and second conductivity type, respectively, first...
8941092 Method for forming semiconductor device structure and semiconductor device  
Disclosed are a method which improves the performance of a semiconductor element, and a semiconductor element with improved performance. The method for forming a semiconductor element structure...
8927361 High threshold voltage NMOS transistors for low power IC technology  
Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively...
8927363 Integrating channel SiGe into pFET structures  
A structure including nFET and pFET devices is fabricated by depositing a germanium-containing layer on a crystalline silicon layer. The crystalline silicon layer is converted to silicon germanium...
8907423 Method of manufacturing a semiconductor device and the semiconductor device  
A high withstand voltage transistor is formed in a high withstand voltage region, and a low withstand voltage transistor is formed in a low withstand voltage region in a method of manufacturing a...
8906767 Semiconductor device with self-aligned interconnects  
A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device...
8900918 Graphene channel-based devices and methods for fabrication thereof  
Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on...
8877579 Methods of manufacturing semiconductor devices  
Methods of manufacturing semiconductor devices include providing a substrate including a NMOS region and a PMOS region, implanting fluorine ions into an upper surface of the substrate, forming a...
8871583 Semiconductor device and manufacturing method thereof  
A non-planar JFET device having a thin fin structure is provided. A fin is formed projecting upwardly from or through a top surface of a substrate, where the fin has a first semiconductor layer...
8859360 Method of manufacturing semiconductor device with offset sidewall structure  
A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and...
8853025 FinFET/tri-gate channel doping for multiple threshold voltage tuning  
An embodiment method of controlling threshold voltages in a fin field effect transistor (FinFET) includes forming a dummy gate over a central portion of a fin, the central portion of the fin...
8829623 Semiconductor memory device  
According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: a contact region; a select gate region; and a memory...
8829616 Method and structure for body contacted FET with reduced body resistance and source to drain contact leakage  
A semiconductor device and method of making same. The device includes a substrate comprising a semiconductor layer on an insulating layer, the semiconductor layer including a semiconductor body...
8822280 Semiconductor device and method of manufacturing semiconductor device  
A first transistor includes a first impurity layer of a first conduction type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first...
8778753 Methods of fabricating semiconductor devices  
A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper...
8765544 Fabrication of a semiconductor device having an enhanced well region  
An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes an enhanced well region to effectively increase a voltage at which...
8759872 Transistor with threshold voltage set notch and method of fabrication thereof  
A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow...
8753932 Asymmetric silicon-on-insulator SRAM cell  
A memory cell having N transistors including at least one pair of access transistors, one pair of pull-down transistors, and one pair of pull-up transistors to form a memory cell, wherein N is an...
8748245 Semiconductor-on-insulator integrated circuit with interconnect below the insulator  
An integrated circuit fabricated on a semiconductor-on-insulator transferred layer is described. The integrated circuit includes an interconnect layer fabricated on the back side of the insulator....
8741720 Penetrating implant for forming a semiconductor device  
A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either...
8722486 Enhancing deposition uniformity of a channel semiconductor alloy by forming a recess prior to the well implantation  
When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby...
8697498 Methods of manufacturing three dimensional semiconductor memory devices using sub-plates  
A method of manufacturing a Three Dimensional (3D) semiconductor memory device can be provided by forming at least one trench in a plate stack structure to divide the plate stack structure into a...
8691653 Semiconductor structure with reduced surface field effect and manufacturing process thereof  
A semiconductor structure and a manufacturing process thereof are disclosed. The semiconductor structure includes a substrate having a first conductive type, a first well having a second...
8680623 Techniques for enabling multiple Vt devices using high-K metal gate stacks  
Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a...
8673720 Structure and fabrication of field-effect transistor having nitrided gate dielectric layer with tailored vertical nitrogen concentration profile  
An insulated-gate field-effect transistor (110, 114, or 122) is fabricated so that its gate dielectric layer (500, 566, or 700) contains nitrogen having a vertical concentration profile specially...
8659054 Method and structure for pFET junction profile with SiGe channel  
A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the...
8647939 Non-relaxed embedded stressors with solid source extension regions in CMOS devices  
A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall...
8643117 Semiconductor device, method for manufacturing same, and semiconductor storage device  
In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET...
8642418 Method of manufacturing semiconductor device with offset sidewall structure  
A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and...
8633083 Apparatus and method for a metal oxide semiconductor field effect transistor with source side punch-through protection implant  
A metal oxide semiconductor field effect transistor (MOSFET) with source side punch-through protection implant. Specifically, the MOSFET comprises a semiconductor substrate, a gate stack formed...
8633550 Semiconductor device  
To improve reliability of a semiconductor device A power MOSFET for switching and a sense MOSFET having an area smaller than that of the power MOSFET and configured to detect an electric current...
8610220 Semiconductor device with self-aligned interconnects  
A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device...
8609496 Method of fabricating semiconductor device comprising a dummy well  
Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can include first transistors that include a first gate insulating layer having a...
8592270 Non-relaxed embedded stressors with solid source extension regions in CMOS devices  
A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall...
8580632 Semiconductor device and method of manufacturing same  
To provide a semiconductor device and a method of manufacturing the same capable of suppressing, when a plurality of MIS transistors having different absolute values of threshold voltage is used,...
8574977 Method for manufacturing stack structure of PMOS device and adjusting gate work function  
The present disclosure provides a method for manufacturing a gate stack structure and adjusting a gate work function for a PMOS device, comprising: growing an ultra-thin interface oxide layer or...
8574976 Semiconductor device and manufacturing method thereof  
A TFT having a high threshold voltage is connected to the source electrode of each TFT that constitutes a CMOS circuit. In another aspect, pixel thin-film transistors are constructed such that a...
8569128 Semiconductor structure and method of fabrication thereof with mixed metal types  
A semiconductor structure includes a first PMOS transistor element having a gate region with a first gate metal associated with a PMOS work function and a first NMOS transistor element having a...
8569800 Field effect transistor  
A field effect transistor includes: a buffer layer that is formed on a substrate; a high resistance layer or a foundation layer that is formed on the buffer layer; a carbon-containing carrier...
8557652 Application of cluster beam implantation for fabricating threshold voltage adjusted FETs  
Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high...
8541272 Method of manufacturing semiconductor device with offset sidewall structure  
A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and...
8536000 Method for producing a semiconductor device have fin-shaped semiconductor regions  
First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r1′ of the upper corner of...