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7632732 Method of manufacturing MOS transistor  
A method of manufacturing a transistor may include: forming a first well over a silicon substrate; forming a first mask pattern over the silicon substrate and using the formed first mask pattern to...
7622356 Method of fabricating metal oxide semiconductor field effect transistor  
There are provided a method for fabricating a MOSFET. The method includes: substrate, forming a semiconductor substrate, a germanium layer by implanting germanium (Ge) ions into a semiconductor...
7595532 Semiconductor memory devices and methods of forming the same  
A semiconductor memory device includes a semiconductor substrate including an insulating layer, a charge storage region of a first conductivity type on the insulating layer, and an insulating film...
7579226 Thin layer element and associated fabrication process  
A method is provided for fabricating a thin layer element, in which a layer of a first material supports a pattern of a second material having a thickness of less than 15 nm, including a step of...
7569449 Processes providing high and low threshold p-type and n-type transistors  
Methods of fabricating negative-channel metal-oxide semiconductor (NMOS) devices and positive-channel metal-oxide semiconductor (PMOS) devices having complementary threshold voltages are described....
7569445 Semiconductor device with constricted current passage  
A semiconductor device including a gate located over a semiconductor substrate and a source/drain region located adjacent the gate. The source/drain region is bounded by an isolation structure that...
7563682 LDMOS transistor device, integrated circuit, and fabrication method thereof  
An LDMOS transistor device in an integrated circuit comprises a semiconductor substrate ( 10 ), a gate region ( 1 ) including a gate semiconductor layer region ( 2; 2′; 151 ) on top of a gate...
7560312 Void formation for semiconductor junction capacitance reduction  
Semiconductor structures having a decreased semiconductor junction capacitance of a semiconductor junction within an active semiconductor layer may be fabricated using an ion implantation and...
7550357 Semiconductor device and fabricating method thereof  
A semiconductor device with a low drain current in the off-state of LDD type accommodating high voltages is provided. On the thermal oxide film, a polysilicon film and a CVD oxide film, and a...
7531404 Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer  
A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal...
7528030 Semiconductor device comprising at least one MOS transistor having an etch stop layer, and corresponding fabrication process  
A semiconductor device includes at least one MOS transistor, each transistor being provided with a source region and a drain region formed in a semiconductor substrate, along with a gate region and...
7504327 Method of manufacturing thin film semiconductor device  
In the invention, a low concentration impurity region is formed between a channel formation region and a source region or a drain region in a semiconductor layer and covered with a gate electrode...
7488635 Semiconductor structure with reduced gate doping and methods for forming thereof  
A semiconductor structure includes a substrate having a memory region and a logic region. A first p-type device is formed in the memory region and a second p-type device is formed in the logic...
7479418 Methods of applying substrate bias to SOI CMOS circuits  
The present invention relates to methods for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a...
7473591 Transistor with strain-inducing structure in channel  
Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is...
7449379 Semiconductor device and method for fabricating the same  
On an insulation layer 12 formed on a silicon substrate 10 , there are formed in an NMOS transistor region 16 an NMOS transistor 14 comprising a silicon layer 34 , a lattice-relaxed silicon...
7446003 Manufacturing process for lateral power MOS transistors  
A process manufactures power MOS lateral transistors together with CMOS devices on a semiconductor substrate. The process forms a lateral MOS transistor having a gate electrode on the semiconductor...
7442600 Methods of forming threshold voltage implant regions  
The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of...
7432141 Large-grain p-doped polysilicon films for use in thin film transistors  
A method is disclosed to form a large-grain, lightly p-doped polysilicon film suitable for use as a channel region in thin film transistors. The film is preferably deposited lightly in situ doped...
7407850 N+ poly on high-k dielectric for semiconductor devices  
The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region ( 304 ) is formed within a semiconductor...
7402495 Method for manufacturing a semiconductor device  
A method of manufacturing a semiconductor device includes forming a first semiconductor region of a first conductive type and a second semiconductor region of a second conductive type in a...
7390719 Method of manufacturing a semiconductor device having a dual gate structure  
A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed...
7368342 Semiconductor device and method of manufacturing the same  
A method for manufacturing a semiconductor device includes forming a gate-insulating film on a semiconductor substrate; forming a gate electrode on the gate-insulating film to be electrically...
7364957 Method and apparatus for semiconductor device with improved source/drain junctions  
A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a...
7361540 Method of reducing noise disturbing a signal in an electronic device  
Certain aspects of a method for reducing noise disturbing at least one signal in an electronic device may comprise shielding a first layer doped with a first dopant from a signaling layer employing...
7354817 Semiconductor device, manufacturing method thereof, and CMOS integrated circuit device  
A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first...
7351627 Method of manufacturing semiconductor device using gate-through ion implantation  
Disclosed herein is a method of manufacturing a semiconductor device via gate-through ion implantation, comprising forming a gate stack on a semiconductor substrate and performing ion implantation...
7329910 Semiconductor substrates and field effect transistor constructions  
The invention includes methods of forming field effect transistor gates. In one implementation, a series of layers is formed proximate a semiconductive material channel region. The layers comprise...
7297584 Methods of fabricating semiconductor devices having a dual stress liner  
In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on...
7297583 Method of making strained channel CMOS transistors having lattice-mismatched epitaxial  
A method is provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a first single-crystal semiconductor region...
7291527 Work function control of metals  
Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second...
7279430 Process for fabricating a strained channel MOSFET device  
A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to...
7268033 Method and structure for providing tuned leakage current in CMOS integrated circuits  
A field effect transistor (FET) comprising an isolation layer, a source region positioned over the isolation layer, a drain region positioned over the isolation layer, a bifurcated silicide gate...
7265011 Method of manufacturing a transistor  
A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor...
7259072 Shallow low energy ion implantation into pad oxide for improving threshold voltage stability  
A method is described to fabricate a MOSFET device with increased threshold voltage stability. After the pad oxide and pad nitride are deposited on the silicon substrate and shallow trenches are...
7244642 Method to obtain fully silicided gate electrodes  
The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer ( 510 ) over a spacer material ( 415 ) located...
7238563 Semiconductor device having isolation region and method of manufacturing the same  
A trench isolation region is formed in a surface region of a semiconductor substrate to form a MOS type element region. A mask layer having an opening portion is formed on the semiconductor layer,...
7232733 Method of forming an integrated circuit incorporating higher voltage devices and low voltage devices therein  
A method of forming an integrated circuit configured to accommodate higher voltage and low voltage devices. In one embodiment, the method of forming the integrated circuit includes forming a...
7223663 MOS transistors and methods of manufacturing the same  
MOS transistors having a low junction capacitance between their halo regions and their source/drain extension regions and methods for manufacturing the same are disclosed. A disclosed MOS...
7220636 Process for controlling performance characteristics of a negative differential resistance (NDR) device  
A variety of processes are disclosed for controlling NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (V NDR ) and related parameters. The processes are...
7217624 Non-volatile memory device with conductive sidewall spacer and method for fabricating the same  
The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate...
7217622 Semiconductor device and method of manufacturing the semiconductor device  
In a method of manufacturing a semiconductor device to improve structural stability of a semiconductor device in a silicidation process, a substrate is provided to have an active region defined by...
7217612 Manufacturing method for a semiconductor device with reduced local current  
A semiconductor device including: a first gate insulating film which is pattern-formed on an N type well region within a P type semiconductor substrate; a second gate insulating film which is...
7214591 Method of fabricating high-voltage MOS device  
A HV-MOS device is described, including a substrate, a gate dielectric layer and a gate, a channel region, two doped regions as a source and a drain, a field isolation layer between the gate and at...
7205185 Self-aligned planar double-gate process by self-aligned oxidation  
A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at...
7195967 Nonvolatile semiconductor memory device and manufacturing method thereof  
In a channel region between the source/drain diffusion layers, impurities of the same conductivity type as the well are doped in an area apart from the diffusion regions. By using as a mask the...
7195968 Method of fabricating semiconductor device  
A method of fabricating a semiconductor device includes forming a resist pattern so that an opening between select gates of a select gate transistor is formed in a memory cell region, implanting...
7179702 Semiconductor device including metal insulator semiconductor field effect transistor and method of manufacturing the same  
A semiconductor device comprises a semiconductor substrate, an N-channel MISFET and a P-channel MISFET provided on the semiconductor substrate, each of the N- and P-channel MISFETs being isolated...
7180107 Method of fabricating a tunneling nanotube field effect transistor  
A method of fabricating a tunneling nanotube field effect transistor includes forming in a nanotube an n-doped region and a p-doped region which are separated by an undoped channel region of the...
7129533 High concentration indium fluorine retrograde wells  
A method and apparatus to form a high-concentration, indium-fluorine retrograde well within a substrate. The indium-fluorine retrograde well includes an indium concentration greater than about...
Matches 1 - 50 out of 372 1 2 3 4 5 6 7 8 >