Patents in Class 438/212

Matches 1 - 50 out of 196

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Match	Document	Document Title
1	7625793	Power MOS device with improved gate charge performance A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor with an improved gate structure. The gate structure includes a first portion of a first conductivity type for...
2	7618865	Method in the fabrication of a monolithically integrated vertical device on an SOI substrate A method in the fabrication of a monolithically integrated vertical device on an SOI substrate comprises the steps of providing an SOI substrate including, from bottom to top, a silicon bulk...
3	7612431	Trench polysilicon diode Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second...
4	7611936	Method to control uniformity/composition of metal electrodes, silicides on topography and devices using this method A method for depositing metals on surfaces is provided which comprises (a) providing a substrate ( 103 ) having a horizontal surface ( 107 ) and a vertical surface ( 105 ); (b) depositing a first...
5	7605034	Integrated circuit memory cells and methods of forming An integrated circuit memory cell includes a combined first capacitor electrode and first transistor source/drain, a second capacitor electrode, a capacitor dielectric between the first and second...
6	7588977	Method of fabricating a MOS field effect transistor having plurality of channels A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are...
7	7585711	Semiconductor-on-insulator (SOI) strained active area transistor A selectively strained MOS device such as selectively strained PMOS device making up an NMOS and PMOS device pair without affecting a strain in the NMOS device the method including providing a...
8	7585705	Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD...
9	7582519	Method of forming a trench structure having one or more diodes embedded therein adjacent a PN junction A semiconductor structure is formed as follows. A semiconductor region is formed to have a P-type region and a N-type region forming a PN junction therebetween. A first trench is formed extending...
10	7569489	High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a...
11	7566619	Methods of forming integrated circuit devices having field effect transistors of different types in different device regions A method of forming an integrated circuit device includes forming a non-planar field-effect transistor in a cell array portion of a semiconductor substrate and forming a planar field-effect...
12	7563665	Semiconductor device and method for manufacturing semiconductor device To laminate field effect transistors having different conductivity types, while suppressing deterioration of the crystallinity of semiconductor layers where the field effect transistors are formed....
13	7544570	Vertical-type metal insulator semiconductor field effect transistor device, and production method for manufacturing such transistor device In a vertical-type metal insulator field effect transistor device having a first conductivity type drain region layer, a plurality of second conductivity type base regions are produced and arranged...
14	7544545	Trench polysilicon diode Embodiments of the present invention include a method of manufacturing a trench polysilicon diode. The method includes forming a N−(P−) type epitaxial region on a N+(P+) type substrate and...
15	7541640	Vertical field-effect transistor and method of forming the same A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a...
16	7534686	Multi-structured Si-fin and method of manufacture Disclosed is a semiconductor fin construction useful in FinFET devices that incorporates an upper region and a lower region with wherein the upper region is formed with substantially vertical...
17	7531395	Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors Methods of forming layers comprising epitaxial silicon, and methods of forming field effect transistors are disclosed. A method of forming a layer comprising epitaxial silicon includes etching an...
18	7528022	Method of forming fin field effect transistor using damascene process A method of forming a fin transistor using a damascene process is provided. A filling mold insulation pattern is recessed to expose an upper portion of a fin, and a mold layer is formed. The mold...
19	7521322	Vertical transistors Vertical transistors for memory cells, such as 4F2 memory cells, are disclosed. The memory cells use digit line connections formed within the isolation trench to connect the digit line with the...
20	7518183	Semiconductor device Heightening of breakdown voltage of a trench gate type power MISFET is actualized without increasing the number of manufacturing steps. In the manufacturing method of the semiconductor device...
21	7514324	Selective epitaxy in vertical integrated circuit Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are vertically oriented. These structures have...
22	7482645	Method and structure for making a top-side contact to a substrate A method for forming a semiconductor structure includes the following steps. A starting semiconductor substrate having a top-side surface and a back-side surface is provided. A recess is formed in...
23	7482285	Dual epitaxial layer for high voltage vertical conduction power MOSFET devices The epitaxial silicon junction receiving layer of a power semiconductor device is formed of upper and lower layers. The lower layer has a resistivity of more than that of the upper layer and a...
24	7482218	Low-capacitance input/output and electrostatic discharge circuit for protecting an integrated circuit from electrostatic discharge A transistor formed on a semiconductor substrate of a first conductivity type in a well formed in the substrate and doped with the first conductivity type to an impurity level higher than that of...
25	7473946	CMOS structure and method including multiple crystallographic planes A complementary metal oxide semiconductor (CMOS) structure includes a semiconductor substrate having first mesa having a first ratio of channel effective horizontal surface area to channel...
26	7473596	Methods of forming memory cells An integrated circuit memory cell includes a combined first capacitor electrode and first transistor source/drain, a second capacitor electrode, a capacitor dielectric between the first and second...
27	7465622	Method for making a raised vertical channel transistor device A method for fabricating a vertical channel transistor device is provided. An opening is formed in a dielectric stack comprised of a pad nitride layer and a pad oxide layer. A plurality of...
28	7462532	Method of fabricating high voltage metal oxide semiconductor device A high voltage metal oxide semiconductor device comprising a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an...
29	7456439	Vertical thyristor-based memory with trench isolation and its method of fabrication A semiconductor device may comprise a plurality of memory cells. A memory cell may comprise a thyristor, at least a portion of which is formed in a pillar of semiconductor material. The pillar may...
30	7436022	Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells and a junction barrier Schottky (JBS) area. The semiconductor...
31	7432145	Power semiconductor device with a base region and method of manufacturing same A low on-state resistance power semiconductor device has a shape and an arrangement that increase the channel density and the breakdown voltage The power semiconductor device comprises a plurality...
32	7432134	Semiconductor device and method of fabricating the same A semiconductor device 100 includes an element-forming region having gate electrode 108 formed therein, and a circumferential region formed in the outer circumference of the element-forming...
33	7429523	Method of forming schottky diode with charge balance structure a Schottky diode having a semiconductor region is formed as follows. A plurality of charge control electrodes are formed in the semiconductor region so as to influence an electric field in the...
34	7375408	Fabricating method of a high voltage metal oxide semiconductor device A high voltage metal oxide semiconductor device comprising a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an...
35	7368353	Trench power MOSFET with reduced gate resistance A method for manufacturing a trench type power semiconductor device which includes process steps for forming proud gate electrodes in order to decrease the resistivity thereof.
36	7364997	Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area....
37	7352034	Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a...
38	7341896	Method of manufacturing a vertical MOS transistor In a method of manufacturing a vertical MOS transistor, a body region, a trench, a gate oxide film, a gate electrode, a source region, and a body contact region are successively formed in a...
39	7332386	Methods of fabricating fin field transistors A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and...
40	7323380	Single transistor vertical memory gain cell A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region...
41	7306984	Method of manufacture of a semiconductor integrated circuit device including a plurality of columnar laminates having different spacing in different directions For improving the filing properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are...
42	7291533	Method for production of trench DRAM cells and a trench DRAM cell array with fin field-effect transistors with a curved channel (CFET—curved fets) A method for producing trench DRAM cells, each having a trench capacitor and a fin field-effect transistor with a curved channel (CFET) for addressing the trench capacitor, is described. The memory...
43	7288815	Semiconductor device and manufacturing method thereof A semiconductor device ( 20, 21, 22 ), including: a channel region ( 4 ) of a first conductivity type formed at a surface layer portion of a semiconductor substrate ( 1 ); a source region ( 25 ) of...
44	7276742	Compound semiconductor light emitting device and its manufacturing method A compound semiconductor light emitting device for preparing a chip which improves the light extraction efficiency, enables mounting of easy positioning with only once wire bonding, and leads to a...
45	7271048	Method for manufacturing trench MOSFET A method of manufacturing a trench MOSFET with high cell density is disclosed. The method introduces a sidewall oxide spacer for narrowing the opening of the trench structure, thereby decreasing...
46	7268032	Termination for trench MIS device having implanted drain-drift region A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from...
47	7259052	Manufacture of a semiconductor integrated circuit device including a pluarality of a columnar laminates having different spacing in different directions For improving the filling properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are...
48	7256086	Trench lateral power MOSFET and a method of manufacturing the same A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device...
49	7241655	Method of fabricating a vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and...
50	7235439	Method of forming a MOS-controllable power semiconductor device for use in an integrated circuit A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one...

Matches 1 - 50 out of 196

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