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7585717 Method of manufacturing semiconductor device, semiconductor device and electronic apparatus therefore  
A method for manufacturing a semiconductor device includes: forming a lower gate electrode over a substrate; forming a sacrifice film over the substrate such that the lower gate electrode is...
7465621 Method of fabricating a switching regulator with a high-side p-type device  
A first impurity region of a first type is implanted to have a first surface area on a substrate. A second impurity region of an opposite second type is implanted into a drain region of the...
7445983 Method of manufacturing a semiconductor integrated circuit device  
A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor...
7364960 Methods for fabricating solid state image sensor devices having non-planar transistors  
Methods for fabricating CMOS image sensor devices are provided, wherein active pixel sensors are constructed with non-planar transistors having vertical gate electrodes and channels, which minimize...
7358573 Triple-well CMOS devices with increased latch-up immunity and methods of fabricating same  
A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under...
7285454 Bipolar transistors with low base resistance for CMOS integrated circuits  
Complementary metal-oxide-semiconductor (CMOS) integrated circuits with bipolar transistors and methods for fabrication are provided. A bipolar transistor may have a lightly-doped base region. To...
7217609 Semiconductor fabrication process, lateral PNP transistor, and integrated circuit  
A method in the fabrication of an integrated bipolar circuit comprises the steps of: providing a p-type substrate; forming in the substrate a buried n+-type region and an n-type region above the...
7163856 Method of fabricating a lateral double-diffused mosfet (LDMOS) transistor and a conventional CMOS transistor  
A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the...
7132344 Super self-aligned BJT with base shorted field plate and method of fabricating  
A bipolar junction transistor (BJT) structure and fabrication method are provided in which a doped polysilicon filled trench is utilized to form both the extrinsic base contact region and a...
7115460 Standard cell back bias architecture  
An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped...
7029938 Method for forming patterns on a semiconductor device using a lift off technique  
Upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA 1 and a region in...
7001806 Semiconductor structure with increased breakdown voltage and method for producing the semiconductor structure  
A semiconductor structure comprises a buried first semiconductor layer of a first doping type, a second semiconductor layer of the first doping type on the buried semiconductor layer, which is less...
6987039 Forming lateral bipolar junction transistor in CMOS flow  
A method of forming a lateral bipolar transistor without added mask in CMOS flow including a p-substrate; patterning and n-well implants; pattern and implant pocket implants for core nMOS and MOS;...
6815282 Silicon on insulator field effect transistor having shared body contact  
Silicon on insulator (SOI) field effect transistors (FET) with a shared body contact, a SRAM cell and array including the SOI FETs and the method of forming the SOI FETs. The SRAM cell has a hybrid...
6784065 Bipolar transistor with ultra small self-aligned polysilicon emitter and method of forming the transistor  
A low-power bipolar transistor is formed to have an intrinsic emitter region with a sub-lithographic width, and an oxide layer that is self aligned to an overlying extrinsic emitter. The small...
6767779 Asymmetrical MOSFET layout for high currents and high speed operation  
A structure and method for a field effect transistor capable of handling high currents, comprises interleaved source and drain diffusion regions with drain diffusion contacts to a first metal level...
6750109 Halo-free non-rectifying contact on chip with halo source/drain diffusion  
A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion...
6692994 Method for manufacturing a programmable chalcogenide fuse within a semiconductor device  
A method for manufacturing a programmable chalcogenide fuse within a semiconductor device is disclosed. A resistor is initially formed on a substrate. Then, a chalcogenide fuse is formed on top of...
6667202 Semiconductor device and method for making the same  
A semiconductor device which has: a bipolar transistor having a collector region of a second conductivity type formed from the surface of a semiconductor substrate of a first conductivity type, a...
6638824 Metal gate double diffusion MOSFET with improved switching speed and reduced gate tunnel leakage  
A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor ( 10 ) with a metal gate ( 26 ). A sacrificial gate layer is patterned to provide a self-aligned source mask. The...
6616786 Process for applying an ink-only label to a polymeric surface  
The invention is directed to a returnable plastic crate provided on at least one surface with an ink only label that is removable without destructive treatment of the said surface, said label being...
6570240 Semiconductor device having a lateral bipolar transistor and method of manufacturing same  
In order to form a semiconductor device including a lateral bipolar transistor which is a match in the device performance for a vertical bipolar transistor, an electrically conductive film which is...
6551869 Lateral PNP and method of manufacture  
A lateral PNP is disclosed in which a substrate of a first conductivity type is used. On top of the substrate a buried region of a second conductivity type is formed. A lightly doped collector...
6528374 Method for forming dielectric stack without interfacial layer  
A method of forming a dielectric stack device having a plurality of layers comprises the steps of providing a silicon substrate, forming a metal-oxide layer on a silicon oxide layer which is formed...
6495407 Method of making an article comprising an oxide layer on a GaAs-based semiconductor body  
A novel method of forming a GaAs-based MOS structure comprises ion implantation after oxide formation, and subsequent slow heating and cooling, carried out such that essentially no interfacial...
6468825 Method for producing semiconductor temperature sensor  
A method for producing a semiconductor temperature sensor comprises the steps of forming PNP bipolar transistors and PMOS transistors so that a base region of each of the PNP bipolar transistors...
6440788 Implant sequence for multi-function semiconductor structure and method  
A multi-function semiconductor device is provided. The device includes a bipolar transistor and an FET formed in parallel. A semiconductor substrate is provided on an insulating layer. A...
6410377 Method for integrating CMOS sensor and high voltage device  
The present invention provides a method for integrating the fabrication of a sensor and a high voltage devices. The N conductive type sensor has a P conductive type doped region in the substrate of...
6372595 Lateral bipolar junction transistor with reduced parasitic current loss  
A semiconductor process is disclosed which forms openings in a dielectric layer through which the emitter region and collector region of lateral bipolar junction transistors are formed. In one...
6365448 Structure and method for gated lateral bipolar transistors  
An improved structure and method for gated lateral bipolar transistors is provided. The present invention capitalizes on opposing sidewall structures and adjacent conductive sidewall members to...
6362034 Method of forming MOSFET gate electrodes having reduced depletion region growth sensitivity to applied electric field  
A method of fabricating a FET having a gate electrode with reduced susceptibility to the carrier depletion effect, includes increasing the amount of n-type dopant in the gate electrode of an...
6326253 Method for fabricating semiconductor device including MIS and bipolar transistors  
After an oxide film has been completely removed from the surface of a substrate by dip etching, the substrate is inserted into a furnace at a temperature as low as about 400° C. to deposit an...
6300669 Semiconductor integrated circuit device and method of designing same  
A semiconductor integrated circuit device comprises a multiple-stage amplifier including a plurality of transistors. The multiple-stage amplifier has a first stage comprising a plurality of bipolar...
6281060 Method of manufacturing a semiconductor device containing a BiCMOS circuit  
A structure of a BiCMOS transistor hindering over-etching of source/drain regions of a MOS transistor and a manufacturing method thereof are provided. A polysilicon film that is to be a gate...
6271069 Method of making an article comprising an oxide layer on a GaAs-based semiconductor body  
Disclosed are a method of making GaAs-based enhancement-type MOS-FETs, and articles (e.g., GaAs-based ICs) that comprise such a MOS-FET. The MOS-FETs are planar devices, without etched recess or...
6249031 High gain lateral PNP and NPN bipolar transistor and process compatible with CMOS for making BiCMOS circuits  
A method and lateral bipolar transistor structure are achieved, with high current gain, compatible with CMOS processing to form BiCMOS circuits. Making a lateral PNP bipolar involves forming an N -...
6245609 High voltage transistor using P+ buried layer  
A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer...
6174779 Method for manufacturing a lateral bipolar transistor  
In a lateral bipolar transistor, its emitter region, base region, link base region, and so forth, are made in self alignment with side walls of masks by using partly overlapping two mask patterns....
6127236 Method of forming a lateral bipolar transistor  
A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a...
6117718 Method for forming BJT via formulation of high voltage device in ULSI  
A method for forming bipolar junction transistor with high gain via formulation of high voltage device in deep submicron process is disclosed. A substrate including a first part, a second part, and...
6093613 Method for making high gain lateral PNP and NPN bipolar transistor compatible with CMOS for making BICMOS circuits  
A method and lateral bipolar transistor structure are achieved, with high current gain, compatible with CMOS processing to form BiCMOS circuits. Making a lateral PNP bipolar involves forming an N -...
6037630 Semiconductor device with gate electrode portion and method of manufacturing the same  
A first polysilicon film which contains phosphorus as an impurity is formed on a semiconductor substrate. A second polysilicon film which is higher in phosphorus concentration than the first...
5869366 Method for forming voltage clamp having a breakdown voltage of 40 Vdc  
An IC voltage clamp and a process for forming the voltage clamp. The voltage clamp includes an MGFO device having an n-type source region, an n-type drain region, and a p-type field implant...
5846858 SOI-BiCMOS method  
In a manufacturing method for lateral bipolar transistors on an SOI substrate, a ridge-shaped gate electrode (8/9) is applied onto a mesa (3) provided with a basic doping and is covered...
5728613 Method of using an insulator spacer to form a narrow base width lateral bipolar junction transistor  
A process has been developed in which narrow base width, lateral bipolar junction transistors, and narrow channel length MOSFET devices, can be simultaneously fabricated, in a silicon on insulator...
5641692 Method for producing a Bi-MOS device  
A method for producing a semiconductor device which decrease the number of processes at the time of producing BiCMOSLSI than the usual. Impurities are introduced into a semiconductor substrate...
5624856 Method for forming a lateral bipolar transistor  
A lateral bipolar transistor comprising a self-aligned polysilicon base contact, and polysilicon emitter and collector contacts is provided. The self-aligned base contact significantly reduces the...
5614424 Method for fabricating an accumulated-base bipolar junction transistor  
This invention describes an accumulated base bipolar junction transistor and an application of the accumulated base transistor as an input stage to an operational amplifier. The accumulated base...
5538908 Method for manufacturing a BiCMOS semiconductor device  
A semiconductor BiCMOS device and method of manufacturing suitable for attaining high packing density and thereby speeding up a switching operation, wherein the device is formed to have one of a...
5416031 Method of producing Bi-CMOS transistors  
In production of a Bi-CMOS semiconductor device, when forming a lateral PNP transistor in a bipolar section, an oxide film is deposited on this base area to prevent etching damages such as those in...
Matches 1 - 50 out of 68 1 2 >