Patents in Class 438/199

Matches 1 - 50 out of 906

Match	Document	Document Title
1	7616120	Multiple RF-port modulator for RFID tag Apparatus and systems may include integrated circuits for use with Radio Frequency Identification (RFID) tags having an antenna structure with at least three coupling ends. The integrated circuits...
2	7615806	Method for forming a semiconductor structure and structure thereof Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality...
3	7615435	Semiconductor device and method of manufacture A semiconductor device and method of manufacture and, more particularly, a semiconductor device having strain films and a method of manufacture. The device includes an embedded SiGeC layer in...
4	7615434	CMOS device and fabricating method thereof A CMOS device is provided, comprising a substrate, a first-type MOS transistor, a second-type MOS transistor, a first stress layer, a first liner layer, and a second stress layer. The substrate has...
5	7615433	Double anneal with improved reliability for dual contact etch stop liner scheme A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere....
6	7615432	HDP/PECVD methods of fabricating stress nitride structures for field effect transistors A stress nitride structure is formed on an integrated circuit field effect transistor by high density plasma (HDP) depositing a first stress nitride layer on the integrated circuit field effect...
7	7615431	Manufacturing method of semiconductor device Before applying a resist on a first gate insulating film, a thinner is provided on an entire surface including a surface of the first gate insulating film to wash the surface of the first gate...
8	7615430	Field effect transistor and method of manufacturing a field effect transistor The invention relates to a method of manufacturing a field effect transistor, in which a semiconductor body of silicon is provided at a surface thereof with a source region and a drain region of a...
9	7615427	Spacer-less low-k dielectric processes A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment...
10	7615402	Electrostatically operated tunneling transistor A transistor operated by changing the electrostatic potential of an island disposed between two tunnel junctions. The transistor has an island of material which has a band gap (e.g. semiconductor...
11	7611951	Method of fabricating MOS transistor having epitaxial region Example embodiments relate to a method of manufacturing a semiconductor device. Other example embodiments relate to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor having an...
12	7611943	Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation A process ( 200 ) for making integrated circuits with a gate, uses a doped precursor ( 124, 126 N and/or 126 P) on barrier material ( 118 ) on gate dielectric ( 116 ). The process ( 200 ) involves...
13	7611939	Semiconductor device manufactured using a laminated stress layer There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers...
14	7611938	Semiconductor device having high drive current and method of manufacture therefor A method comprises forming a first semiconductor device in a substrate, where the first semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the...
15	7611935	Gate straining in a semiconductor device Gate straining techniques as described herein can be utilized during the fabrication of NMOS transistor devices, PMOS transistor devices, or CMOS device structures. For an NMOS device, conductive...
16	7611922	Image sensor and method for manufacturing the same A method for manufacturing an image sensor includes forming first to third photodiodes and first to third color filters corresponding thereto; forming a photoresist film including photosensitive...
17	7608501	Technique for creating different mechanical strain by forming a contact etch stop layer stack having differently modified intrinsic stress By partially removing an etch stop layer prior to the formation of a first contact etch stop layer, a superior stress transfer mechanism may be provided in an integration scheme for generating...
18	7608499	Semiconductor structure comprising field effect transistors with stressed channel regions and method of forming the same A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. Each of the first transistor...
19	7608476	Electronic device A technique for high-resolution surface energy assisted patterning of semiconductor active layer islands on top of an array of predefined source-drain electrodes without requiring an additional...
20	7605447	Highly manufacturable SRAM cells in substrates with hybrid crystal orientation The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down...
21	7598542	SRAM devices and methods of fabricating the same SRAM devices and methods of fabricating the same are disclosed, by which a process margin and a degree of device integration are enhanced by reducing the number of contact holes of an SRAM device...
22	7598540	High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the same The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present...
23	7598142	CMOS device with dual-epi channels and self-aligned contacts A CMOS device having dual-epi channels comprises a first epitaxial region formed on a substrate, a PMOS device formed on the first epitaxial region, a second epitaxial region formed on the...
24	7595234	Fabricating method for a metal oxide semiconductor transistor A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the...
25	7595233	Gate stress engineering for MOSFET Methods of stressing a channel of a transistor as a result of a material volume change in a gate structure and a related structure are disclosed. In one embodiment, a method includes forming a gate...
26	7595231	Semiconductor device and its manufacture In a logic area, impurities are doped into the gate electrode and the source/drain diffusion regions of a MIS transistor. Thereafter in a memory cell area, word lines are patterned, source/drain...
27	7595230	Thin film transistor, method of manufacturing same, display device, method of modifying an oxide film, method of forming an oxide film, semiconductor device, method of manufacturing semiconductor device, and apparatus for manufacturing semiconductor device In a manufacturing method of a thin film transistor ( 1 ), the oxide film forming step is performed whereby: a process-target substrate ( 2 ) having a surface on which a gate oxide film ( 4 )...
28	7595210	Method of manufacturing complementary metal oxide semiconductor image sensor A method of manufacturing a complementary metal oxide semiconductor (CMOS) image sensor is provided. The method can include the steps of: providing a semiconductor substrate having an active region...
29	7592270	Modulation of stress in stress film through ion implantation and its application in stress memorization technique Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is...
30	7592214	Method of manufacturing a semiconductor device including epitaxially growing semiconductor epitaxial layers on a surface of semiconductor substrate A semiconductor device has a first MOS transistor formed on first active region of the first conductivity type, having first gate electrode structure, first source/drain regions, recesses formed in...
31	7589386	Semiconductor device and manufacturing method thereof A semiconductor device including a first field effect transistor having a source, a first conductivity type drain, a gate, and a first conductivity type channel layer formed beneath the gate and...
32	7586160	Method of manufacturing a semiconductor integrated circuit and semiconductor integrated circuit A semiconductor integrated circuit is provided in which a CMOS transistor is formed on a first conductivity type semiconductor film provided on a first conductivity type supporting substrate...
33	7585720	Dual stress liner device and method A dual stress liner manufacturing method and device is described. Overlapping stress liner layers of opposite effect (e.g., tensile versus compression) may be deposited over portions of the device,...
34	7582521	Dual metal gates for mugfet device Exemplary embodiments provide methods and structures for controlling work function values of dual metal gate electrodes for transistor devices. Specifically, the work function value of one of the...
35	7579660	Semiconductor device and manufacturing method thereof A semiconductor device includes a substrate including a semiconductor layer at a surface, a gate insulating film disposed on the semiconductor layer, and a gate electrode disposed on the gate...
36	7579229	Semiconductor device and semiconductor substrate In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of...
37	7579228	Disposable organic spacers A method for making a semiconductor device is provided, comprising (a) providing a semiconductor structure comprising a first gate electrode ( 210 ); (b) forming a first set of organic spacers (...
38	7575969	Buried layer and method A high resistivity silicon for RF passive operation including CMOS structures with implanted CMOS wells and a buried layer under the wells formed by deep implants during well implantations.
39	7575968	Inverse slope isolation and dual surface orientation integration A semiconductor process and apparatus provide a high performance CMOS devices ( 108, 109 ) with hybrid or dual substrates by etching a deposited oxide layer ( 62 ) using inverse slope isolation...
40	7572692	Complementary transistors having different source and drain extension spacing controlled by different spacer sizes Disclosed is a method of forming an integrated circuit structure having first-type transistors, such as P-type field effect transistors (PFETs) and complementary second-type transistors, such as...
41	7572690	Method of fabricating CMOS thin film transistor (TFT) and CMOS TFT fabricated using the same A method of fabricating a CMOS thin film transistor (TFT) and a CMOS TFT fabricated using the method involve provision of a substrate having a first region and a second region. A first...
42	7572689	Method and structure for reducing induced mechanical stresses Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the...
43	7569455	Manufacturing method of semiconductor device A manufacturing method of a CMOS semiconductor device includes using, in an nMOS, spike RTA (first annealing) together with ultra-rapid rising/falling temperature annealing (second annealing) whose...
44	7569447	Method of forming transistor structure having stressed regions of opposite types A method of fabrication is provided in which a field effect transistor (FET) is formed having a channel region and source and drain regions adjacent to the channel region. A first stressed region...
45	7569446	Semiconductor structure and method of manufacture A complimentary metal oxide semiconductor and a method of manufacturing the same using a self-aligning process to form one of the stacks of device. The method includes depositing an oxide layer...
46	7569445	Semiconductor device with constricted current passage A semiconductor device including a gate located over a semiconductor substrate and a source/drain region located adjacent the gate. The source/drain region is bounded by an isolation structure that...
47	7569443	Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed...
48	7566606	Methods of fabricating semiconductor devices having strained dual channel layers A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained...
49	7566605	Epitaxial silicon germanium for reduced contact resistance in field-effect transistors A method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described. This increases the electron mobility for the...
50	7566604	Method of fabricating a dual-gate structure that prevents cut-through and lowered mobility A method of fabricating a dual-gate semiconductor device, including forming a first PMOS transistor on a semiconductor substrate, the first PMOS transistor having a first gate electrode and a first...

Matches 1 - 50 out of 906

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