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9281200 Enhanced patterning uniformity of gate electrodes of a semiconductor device by late gate doping  
When forming sophisticated semiconductor-based gate electrode structures of transistors, the pre-doping of one type of gate electrode structure may be accomplished after the actual patterning of...
9041158 Method of forming fin field-effect transistors having controlled fin height  
A semiconductor apparatus includes fin field-effect transistor (FinFETs) having controlled fin heights. The apparatus includes a high fin density area and a low fin density area. Each fin density...
9040373 Silicon device on SI:C-OI and SGOI and method of manufacture  
A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a...
9040372 Niobium and vanadium organometallic precursors for thin film deposition  
Disclosed are methods for forming a metal-containing layer on a substrate. The methods include providing a vapor and at least one reaction gas and reacting the vapor and the reaction gas with the...
9040379 Semiconductor constructions and methods of forming semiconductor constructions  
Some embodiments include methods in which first insulative material is formed across a memory region and a peripheral region of a substrate. An etch stop structure is formed to have a higher...
9041116 Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs)  
A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate...
9035360 Semiconductor device and SiP device using the same  
A semiconductor device includes a logic circuit and an active element circuit. The logic circuit is provided with semiconductor elements formed in a semiconductor substrate. The active element...
9034737 Epitaxially forming a set of fins in a semiconductor device  
Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of...
9034704 6T SRAM architecture for gate-all-around nanowire devices  
A memory device includes a first plurality of semiconductor nanowires tethered between landing pads and suspended over a substrate. A first gate electrode surrounds each of the first plurality of...
9029212 MEMS pressure sensors and fabrication method thereof  
A MEMS capacitive pressure sensor is provided. The pressure sensor includes a substrate having a first region and a second region, and a first dielectric layer formed on the substrate. The...
9029834 Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric  
Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is...
9023688 Method of processing a semiconductor device  
A method for processing a semiconductor device, the method including; providing a first semiconductor layer including first transistors; forming interconnection layers overlying the transistors,...
9023696 Method of forming contacts for devices with multiple stress liners  
Disclosed herein is a method of forming a semiconductor device. In one example, the method includes performing a first process operation to form a first etch stop layer above a first region of a...
9023713 Ultrathin body fully depleted silicon-on-insulator integrated circuits and methods for fabricating same  
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing an ultrathin body (UTB) fully...
9023697 3D transistor channel mobility enhancement  
A method of forming a semiconductor structure includes growing an epitaxial doped layer over an exposed portion of a plurality of fins. The epitaxial doped layer combines the exposed portion of...
9023719 High aspect ratio memory hole channel contact formation  
A method of fabricating a semiconductor device, such as a three-dimensional monolithic NAND memory string, includes etching a select gate electrode over a first gate insulating layer over a...
9018710 Semiconductor device with metal gate and high-k materials and method for fabricating the same  
A semiconductor device includes a substrate including first and second regions. A first gate stack structure containing a first effective work function adjust species is formed over the first...
9018057 Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer  
A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer...
9018711 Selective growth of a work-function metal in a replacement metal gate of a semiconductor device  
Approaches for forming a replacement metal gate (RMG) of a semiconductor device, are disclosed. Specifically provided is a p-channel field effect transistor (p-FET) and an n-channel field effect...
9018086 Semiconductor device having a metal gate and fabricating method thereof  
The present invention provides a method of forming a semiconductor device having a metal gate. A substrate is provided and a gate dielectric and a work function metal layer are formed thereon,...
9012277 In situ doping and diffusionless annealing of embedded stressor regions in PMOS and NMOS devices  
Generally, the present disclosure is directed to methods for forming dual embedded stressor regions in semiconductor devices such as transistor elements and the like, using in situ doping and...
9012999 Semiconductor device with an inclined source/drain and associated methods  
A semiconductor device includes a semiconductor substrate having a channel region therein, a gate structure above the channel region, and source and drain regions on opposite sides of the gate...
9012278 Method of making a wire-based semiconductor device  
In some embodiments, a method for manufacturing forms a semiconductor device, such as a transistor. A dielectric stack is formed on a semiconductor substrate. The stack comprises a plurality of...
9006707 Forming arsenide-based complementary logic on a single substrate  
In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium...
9006094 Stratified gate dielectric stack for gate dielectric leakage reduction  
A stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a...
9000531 Method and manufacture of transistor devices  
A method of forming transistors and structures thereof. A CMOS device includes high k gate dielectric materials. A PMOS device includes a gate that is implanted with an n type dopant. The NMOS...
9000530 6T SRAM architecture for gate-all-around nanowire devices  
A memory device includes a first plurality of semiconductor nanowires tethered between landing pads and suspended over a substrate. A first gate electrode surrounds each of the first plurality of...
8993391 Semiconductor device with recess gate and method for fabricating the same  
A method for fabricating a semiconductor device includes forming a conductive layer over first and second regions of a semiconductor substrate, forming a trench extended in the first region of the...
8994116 Hybrid gate process for fabricating FinFET device  
Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over...
8994097 MOS devices having non-uniform stressor doping  
A device includes a semiconductor substrate, a gate stack over the semiconductor substrate, and a stressor region having at least a portion in the semiconductor substrate and adjacent to the gate...
8987141 Method of manufacturing Si-based high-mobility group III-V/Ge channel CMOS  
A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer...
8987080 Methods for manufacturing metal gates  
Provided are methods for making metal gates suitable for FinFET structures. The methods described herein generally involve forming a high-k dielectric material on a semiconductor substrate;...
8987120 Flat panel display device comprising polysilicon thin film transistor and method of manufacturing the same  
The present invention relates to a flat panel display device comprising a polysilicon thin film transistor and a method of manufacturing the same. Grain sizes of polysilicon grains formed in...
8987081 Method of manufacturing semiconductor device with offset sidewall structure  
A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and...
8980706 Double treatment on hard mask for gate N/P patterning  
The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region, forming first and second gate stacks over the first and second...
8975129 Method of making a FinFET device  
A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. A plurality of mandrel features are formed on a substrate. First spacers are formed along sidewalls of the...
8975703 MOS transistor, formation method thereof, and SRAM memory cell circuit  
Various embodiments provide an MOS transistor, a formation method thereof, and an SRAM memory cell circuit. An exemplary MOS transistor can include a semiconductor substrate including a first...
8975128 Electronic devices and systems, and methods for making and using the same  
Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor...
8969190 Methods of forming a layer of silicon on a layer of silicon/germanium  
Disclosed herein are various methods of forming a layer of silicon on a layer of silicon/germanium. In one example, a method disclosed herein includes forming a silicon/germanium material on a...
8962419 Complementary stress memorization technique layer method  
A process of forming a CMOS integrated circuit by forming a first stressor layer over two MOS transistors of opposite polarity, removing a portion of the first stressor layer from the first...
8962414 Reduced spacer thickness in semiconductor device fabrication  
In aspects of the present disclosure, a reliable encapsulation of a gate dielectric is provided at very early stages during fabrication. In other aspects, a semiconductor device is provided...
8963295 Semiconductor structure with beryllium oxide  
A semiconductor structure with beryllium oxide is provided. The semiconductor structure comprises: a semiconductor substrate (100); and a plurality of insulation oxide layers (201, 202 . . . 20x)...
8962415 Methods of forming gates of semiconductor devices  
Methods of forming gates of semiconductor devices are provided. The methods may include forming a first recess in a first substrate region having a first conductivity type and forming a second...
8957481 Semiconductor structure and method for manufacturing the same  
The present application discloses a semiconductor structure and a method for manufacturing the same. Compared with conventional approaches to form contacts, the present disclosure reduces contact...
8956907 Method for producing field effect transistor, field effect transistor, display device, image sensor, and X-ray sensor  
There is provided a method of fabricating a field effect transistor including: forming a first oxide semiconductor film on a gate insulation layer disposed on a gate electrode; forming a second...
8956948 Shallow trench isolation extension  
A semiconductor device is formed with extended STI regions. Embodiments include implanting oxygen under STI trenches prior to filling the trenches with oxide and subsequently annealing. An...
8951853 Method of forming semiconductor device using Si-H rich silicon nitride layer  
A method of forming a semiconductor device includes forming a gate electrode and source/drain regions in a semiconductor substrate, forming a first capping nitride layer covering the gate...
8951855 Manufacturing method for semiconductor device having metal gate  
A manufacturing method for a semiconductor device having a metal gate is provided. First and second gate trenches are respectively formed in first and second semiconductor devices. A work-function...
8946007 Inverted thin channel mosfet with self-aligned expanded source/drain  
After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a...
8946005 Thin-film transistor, array substrate having the thin-film transistor and method of manufacturing the array substrate  
A thin-film transistor includes a semiconductor pattern, source and drain electrodes and a gate electrode, the semiconductor pattern is formed on a base substrate, and the semiconductor pattern...