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8183104 |
Method for dual-channel nanowire FET device
An apparatus, system, and method for dual-channel FET devices is presented. In some embodiments, the nanowire FET device may include a first transistor on a substrate, where the first transistor...
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8183105 |
Integrated circuit device with stress reduction layer
An integrated circuit device is disclosed that includes a dual stress liner NMOS device having a tensile stress layer that overlies a NMOS gate film stack, a dual stress liner PMOS device having a...
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8183137 |
Use of dopants to provide low defect gate full silicidation
The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming a layer of gate...
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8183118 |
Method for fabricating MOS transistor
The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching...
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8183640 |
Method of fabricating transistors and a transistor structure for improving short channel effect and drain induced barrier lowering
A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well,...
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8183641 |
Semiconductor device and method for manufacturing same
A silicon oxynitride film is formed on entire surface of a semiconductor substrate, a lanthanum oxide film is formed on the silicon oxynitride film and the lanthanum oxide film is removed from a...
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8183642 |
Gate effective-workfunction modification for CMOS
CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same...
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8183605 |
Reducing transistor junction capacitance by recessing drain and source regions
By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately...
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8178402 |
End functionalization of carbon nanotubes
Carbon nanotubes may be selectively opened and their exposed ends functionalized. Opposite ends of carbon nanotubes may be functionalized in different fashions to facilitate self-assembly and other...
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8178401 |
Method for fabricating dual-metal gate device
A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate....
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8178400 |
Replacement spacer for tunnel FETs
A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the...
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8178399 |
Production method for semiconductor device
An SGT production method includes forming a pillar-shaped first-conductive-type semiconductor layer and forming a second-conductive-type semiconductor layer underneath the first-conductive-type...
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8173499 |
Method of fabricating a gate stack integration of complementary MOS device
A method of forming an integrated circuit structure includes providing a substrate comprising a first device region and a second device region; forming an oxide cap over the substrate and in the...
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8168489 |
High performance stress-enhanced MOSFETS using Si:C and SiGe epitaxial source/drain and method of manufacture
A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and...
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8168491 |
Method for fabricating dual poly gate in semiconductor device
A method for fabricating a dual poly gate in a semiconductor device, comprising: forming a gate insulation layer and a polysilicon layer on a semiconductor substrate that defines a first region and...
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8168490 |
Co-packaging approach for power converters based on planar devices, structure and method
A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral dif...
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8168971 |
Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain
The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET,...
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8169033 |
Semiconductor devices and methods of manufacture thereof
Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece,...
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8163607 |
Semiconductor device and method of making the same
In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a NixSi layer at meddle height...
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8163605 |
Production method for semiconductor device
It is intended to provide an SGT production method capable of obtaining a structure for reducing a resistance of a source, drain and gate, a desired gate length, desired source and drain...
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8158473 |
Method for manufacturing a semiconductor device having a silicide region comprised of a silicide of a nickel alloy
To provide a semiconductor device which can reduce an electrical resistance between a plug and a silicide region, and a manufacturing method thereof. At least one semiconductor element having a...
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8159034 |
Semiconductor device having insulated gate field effect transistors and method of manufacturing the same
N-type semiconductor region and P-type semiconductor region are provided in a surface region of a semiconductor substrate. Insulating film and silicon containing film are laminated on the...
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8154319 |
Three-dimensional architecture for integration of CMOS circuits and nano-material in hybrid digital circuits
A hybrid CMOL stack enables more efficient design of CMOS logical circuits. The hybrid CMOL structure includes a first substrate having a CMOS device layer on the substrate, a first interconnect...
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8153498 |
Downsize polysilicon height for polysilicon resistor integration of replacement gate process
A semiconductor device and method for fabricating a semiconductor device protecting a resistive structure in gate replacement processing is disclosed. The method comprises providing a semiconductor...
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8154055 |
CMOS image sensor and method for fabricating the same
A complementary metal-oxide semiconductor (CMOS) image sensor includes a photodiode formed in a substrate structure, first to fourth gate electrodes formed over the substrate structure, spacers...
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8148221 |
Double anneal with improved reliability for dual contact etch stop liner scheme
A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere....
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8143119 |
Method of manufacturing semiconductor device having plural transistors formed in well region and semiconductor device
A first transistor and a second transistor are formed in a first element formation region, and a third transistor is formed in a second element formation region. The three transistors are of the...
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8143082 |
Wafer bonding of micro-electro mechanical systems to active circuitry
A single integrated wafer package includes a micro electromechanical system (MEMS) wafer, an active device wafer, and a seal ring. The MEMS wafer has a first surface and includes at least one MEMS...
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8138030 |
Asymmetric finFET device with improved parasitic resistance and capacitance
A method for forming a fin field effect transistor (finFET) device includes, forming a fin structure in a substrate, forming a gate stack structure perpendicular to the fin structure, and...
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8138038 |
Superior fill conditions in a replacement gate approach by performing a polishing process based on a sacrificial fill material
In a replacement gate approach, a top area of a gate opening may receive a superior cross-sectional shape after the deposition of a work function adjusting species on the basis of a polishing...
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8138055 |
Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same
In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate...
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8138035 |
Method for forming integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels
A method of forming an integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are...
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8138037 |
Method and structure for gate height scaling with high-k/metal gate technology
A method and structure to scale metal gate height in high-k/metal gate transistors. A method includes forming a dummy gate and at least one polysilicon feature, all of which are formed from a same...
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8138036 |
Through silicon via and method of fabricating same
A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the...
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8134152 |
CMOS thin film transistor, method of fabricating the same and organic light emitting display device having laminated PMOS poly-silicon thin film transistor with a top gate configuration and a NMOS oxide thin film transistor with an inverted staggered bottom gate configuration
A CMOS thin film transistor arrangement including a PMOS poly-silicon thin film transistor having a top gate configuration and a NMOS oxide thin film transistor having an inverted staggered bottom...
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8133777 |
Method of fabricating memory
A method of fabricating a memory is provided. A substrate including a memory region and a periphery region is provided. A plurality of gates each having spacers is formed on the substrate. A...
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RE43229 |
Method for manufacturing semiconductor device, including multiple heat treatment
A semiconductor device manufacturing method having forming first and second insulating gate portions spaced from each other on a semiconductor substrate, selectively implanting the first...
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8119473 |
High temperature anneal for aluminum surface protection
The present disclosure also provides another embodiment of a method for making metal gate stacks. The method includes forming a first dummy gate and a second dummy gate on a substrate; removing a...
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8119474 |
High performance capacitors in planar back gates CMOS
A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically...
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8119472 |
Silicon device on Si:C SOI and SiGe and method of manufacture
A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a...
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8120118 |
Semiconductor device and manufacturing method of the same
Provided is a highly reliable semiconductor device equipped with a plurality of semiconductor elements having desired properties, respectively; and a manufacturing method facilitating the...
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8114722 |
Manufacturing method of semiconductor device
To suppress generation of dangling bonds, the present invention relates to a method for manufacturing a semiconductor device including the steps of: forming a semiconductor film; forming a gate...
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8114696 |
CMOS image sensor with asymmetric well structure of source follower
Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having...
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8114784 |
Laminated stress overlayer using In-situ multiple plasma treatments for transistor improvement
Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the...
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8115256 |
Semiconductor device
A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes...
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8114684 |
Vertical hall effect sensor with current focus
A complementary metal oxide semiconductor (CMOS) sensor system in one embodiment includes a doped substrate, a doped central island extending downwardly within the doped substrate from an upper...
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8114727 |
Disposable spacer integration with stress memorization technique and silicon-germanium
An integrated process flow for forming an NMOS transistor (104) and an embedded SiGe (eSiGe) PMOS transistor (102) using a stress memorization technique (SMT) layer (126). The SMT layer (126) is...
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8114728 |
Integration scheme for an NMOS metal gate
A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of the NMOS transistor and the...
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8116121 |
Semiconductor device and manufacturing methods with using non-planar type of transistors
Static random access memory cells and methods of making static random access memory cells are provided. The static random access memory cells contain two non-planar pass-gate transistors, two...
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8114741 |
Oxygen-rich layers underlying BPSG
An integrated circuit structure and a method of forming the same are provided. The method includes providing a surface; performing an ionized oxygen treatment to the surface; forming an initial...
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