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7067368 Method for forming self-aligned dual salicide in CMOS technologies  
A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first...
7067367 Method for reducing poly-depletion due to thickness variation in a polysilicon layer in dual gate CMOS fabrication process  
Disclosed is a method for reducing poly-depletion in a dual gate CMOS fabrication process. The method reduces the poly-depletion in a dual gate CMOS fabrication process by increasing the doping...
7064025 Method for forming self-aligned dual salicide in CMOS technologies  
A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first...
7064027 Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance  
An etch resistant liner covering sidewalls of a transistor gate stack and along a portion of the substrate at a base of the transistor gate stack. The liner prevents silicide formation on the...
7064396 Integrated circuit with multiple spacer insulating region widths  
An integrated circuit with both P-channel transistors ( 823 ) and N-channel transistors ( 821 ) with different spacer insulating region widths. In one example, the outer sidewall spacer ( 321 ) of...
7060549 SRAM devices utilizing tensile-stressed strain films and methods for fabricating the same  
SRAM devices utilizing tensile-stressed strain films and methods for fabricating such SRAM devices are provided. An SRAM device, in one embodiment, comprises an NFET and a PFET that are...
7056782 CMOS silicide metal gate integration  
The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal...
7052946 Method for selectively stressing MOSFETs to improve charge carrier mobility  
A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second...
7052945 Short-channel Schottky-barrier MOSFET device and manufacturing method  
A MOSFET device and method of fabricating are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device...
7045408 Integrated circuit with improved channel stress properties and a method for making it  
An integrated circuit is described that comprises a PMOS transistor and an NMOS transistor that are formed on a semiconductor substrate. A silicate glass layer is formed on only the PMOS transistor...
7045409 Semiconductor device having active regions connected together by interconnect layer and method of manufacture thereof  
A semiconductor device having active regions connected by an interconnect line, which includes first and second transistors each having active regions and formed spaced apart from each other in a...
7045380 CMOS image sensor and method of fabricating the same  
An image sensor and a fabricating method thereof are provided. The image sensor includes a floating diffusion region disposed at a predetermined region of a substrate, a photodiode region, and a...
7041538 Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOS  
A high-performance recessed channel CMOS device including an SOI layer having a recessed channel region and adjoining extension implant regions and optional halo implant regions; and at least one...
7041544 Semiconductor integrated circuit and method for fabricating the same  
First to third logic circuits and first to third static random access memories (SRAMs) are formed on one chip. Power to the first and third logic circuits and their SRAMs is shut off as required,...
7041549 Method for manufacturing semiconductor device  
In a method for manufacturing a semiconductor device, a gate insulating film and a gate electrode are first formed on a substrate. Next, Ge ions, Si ions, or the like are implanted to make the...
7037770 Method of manufacturing strained dislocation-free channels for CMOS  
A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. An SiGe layer is grown in the channel of the nFET...
7033919 Fabrication of dual work-function metal gate structure for complementary field effect transistors  
For fabricating dual gate structures of complementary transistors, a gate material is deposited into an opening disposed over a P-well and an N-well having the complementary transistors formed...
7034407 Semiconductor device and method for fabricating the same  
A substrate 11 consists of a semiconductor layer 12 as an element formation region and an STI 13 as an isolation region. A gate dielectric 15 is provided on the semiconductor layer 12 ,...
7029967 Silicide method for CMOS integrated circuits  
A method for forming metal silicide regions in source and drain regions ( 160, 170 ) is described. Prior to the thermal annealing of the source and drain regions ( 160, 170 ), germanium is...
7026205 Method for manufacturing semiconductor device, including multiple heat treatment  
A semiconductor device manufacturing method having forming first and second insulating gate portions spaced from each other on a semiconductor substrate, selectively implanting the first...
7022561 CMOS device  
A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a...
7022559 MOSFET gate electrodes having performance tuned work functions and methods of making same  
An insulated gate field effect transistor (FET) of a particular conductivity type, has as a gate electrode, a non-semiconductive material with a work function that approximates the work function of...
7018882 Method to form local “silicon-on-nothing” or “silicon-on-insulator” wafers with tensile-strained silicon  
A method of forming a substrate for use in IC device fabrication includes preparing a silicon substrate, including doping a bulk silicon ( 100 ) substrate with ions taken from the group of ions to...
7018889 Latch-up prevention for memory cells  
An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to V CC through parasitic...
7018883 Dual work function gate electrodes  
Methods of manufacturing transistor gate electrodes including, in one embodiment, forming a metal layer over first and second regions of a substrate, wherein the first and second regions have...
7005335 Array of nanoscopic mosfet transistors and fabrication methods  
A nanoscopic transistor is made by forming an oxide layer on a semiconductor substrate, applying resist, patterning the resist using imprint lithography to form a pattern aligned along a first...
7005336 Process for forming CMOS transistors and MOS transistors of the drain extension type, with a low gate region resistance, in the same semiconductor substrate  
A process is disclosed for forming, on a common semiconductor substrate, CMOS transistors and vertical or lateral MOS transistors on at least first and second portions, respectively, of the...
7005342 Method to fabricate surface p-channel CMOS  
An improved method of making CMOS surface channel transistors using fewer masking steps. In-situ doped poly silicon deposition can be used to reduce problems with poly depletion effects in...
7005334 Zero threshold voltage pFET and method of making same  
A zero threshold voltage (ZVt) pFET ( 104 ) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate ( 112 ) with a retrograde n-well ( 116 ) so that a pocket ( 136 )...
6998303 Manufacture method for semiconductor device with patterned film of ZrO2 or the like  
An insulating film made of zirconia or hafnia is formed on the surface of a semiconductor substrate. A partial surface area of the insulating film is covered with a mask pattern. By using the mask...
6998278 Method of fabricating a micro-electromechanical actuator that includes drive circuitry  
A method of fabricating a micro-electromechanical actuator includes the step of forming register, gate and drive transistor circuitry on a substrate such that a number of laterally extending traces...
6998683 TFT-based common gate CMOS inverters, and computer systems utilizing novel CMOS inverters  
Thin film transistor based three-dimensional CMOS inverters utilizing a common gate bridged between a PFET device and an NFET device. One or both of the NFET and PFET devices can have an active...
6995435 Apparatus and circuit having reduced leakage current and method therefor  
Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage generator that selectively increases the voltage potential on the channel region of a transistor...
6995055 Structure of a semiconductor integrated circuit and method of manufacturing the same  
A method of fabricating CMOS transistors of first and second conductivity types in an SOI substrate includes the steps of etching contact holes and alignment marks through the semiconductor and...
6992361 Deep well implant structure providing latch-up resistant CMOS semiconductor product  
A CMOS semiconductor product employs a first doped well of a first polarity and a second doped well of a second polarity opposite the first polarity, each formed laterally separated within a...
6989302 Method for fabricating a p-type shallow junction using diatomic arsenic  
The present invention provides, in one embodiment, a method of fabricating a semiconductor device ( 100 ). The method comprises exposing a portion ( 125 ) of an n-type substrate ( 105 ) to an...
6987039 Forming lateral bipolar junction transistor in CMOS flow  
A method of forming a lateral bipolar transistor without added mask in CMOS flow including a p-substrate; patterning and n-well implants; pattern and implant pocket implants for core nMOS and MOS;...
6987061 Dual salicide process for optimum performance  
The present invention pertains to forming respective silicides on multiple transistors in a single process. High performance is facilitated with simple and highly integrated process flows. As such,...
6982196 Oxidation method for altering a film structure and CMOS transistor structure formed therewith  
A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a...
6982229 Ion recoil implantation and enhanced carrier mobility in CMOS device  
An integrated circuit (IC) includes a CMOS device formed above a semiconductor substrate having ions therein that are implanted in the semiconductor substrate by an ion recoil procedure. The IC...
6982187 Methods of making shallow trench-type pixels for CMOS image sensors  
A method of making a shallow trench-type pixel for a CMOS image sensor is disclosed. The disclosed pixel-fabricating method can increase the active area of a pixel by forming a photodiode in the...
6977194 Structure and method to improve channel mobility by gate electrode stress modification  
In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the...
6974737 Schottky barrier CMOS fabrication method  
A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and...
6974735 Dual layer Semiconductor Devices  
A semiconductor-based device includes a channel layer, which includes a distal layer and a proximal layer in contact with the distal layer. The distal layer supports at least a portion of hole...
6972223 Use of atomic oxygen process for improved barrier layer  
A composite barrier layer formed between a glass film and active regions of a memory device is disclosed. The composite barrier layer comprises an oxide layer formed by atomic deposition process...
6972228 Method of forming an element of a microelectronic circuit  
A method is described for forming an element of a microelectronic circuit. A sacrificial layer is formed on an upper surface of a support layer. The sacrificial layer is extremely thin and uniform....
6972222 Temporary self-aligned stop layer is applied on silicon sidewall  
A method is provided for forming NMOS and PMOS transistors with ultra shallow source/drain regions having high dopant concentrations. First sidewall spacers and nitride spacers are sequentially...
6972224 Method for fabricating dual-metal gate device  
A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric ( 34 ), such as HfO 2 , is deposited on a semiconductor...
6969645 Method of manufacturing a semiconductor device comprising a non-volatile memory with memory cells  
A method of manufacturing a semiconductor device comprising a non-volatile memory with memory cells (Mij) including a select transistor (T 1 ) with a select gate ( 1 ) and including a memory...
6969893 Semiconductor device and portable electronic apparatus  
There is provided a semiconductor device of low power consumption and high reliability having DTMOS' and substrate-bias variable transistors, and portable electronic equipment using the...
Matches 401 - 450 out of 930 < 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 >