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7148143 Semiconductor device having a fully silicided gate electrode and method of manufacture therefor  
The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device ( 100 ), among other possible...
7144767 NFETs using gate induced stress modulation  
A method for manufacturing an integrated circuit comprising a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor by covering the...
7141467 Semiconductor device having metal silicide films formed on source and drain regions and method for manufacturing the same  
A semiconductor device includes a p-type well region, n + -type diffusion regions formed in the surface region of the p-type well region, a gate electrode containing silicon and formed above the...
7138309 Integration of biaxial tensile strained NMOS and uniaxial compressive strained PMOS on the same wafer  
A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compressive strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, includes...
7138312 Semiconductor device and method for fabricating the same  
The semiconductor device comprises a gate interconnection 24 a including a gate electrode formed over a semiconductor substrate 14 with a gate insulation film 22 formed therebetween; a first...
7138310 Semiconductor devices having strained dual channel layers  
A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained...
7135362 Isolation layer for CMOS image sensor and fabrication method thereof  
The present invention relates to an isolation layer for CMOS image sensor and a fabrication method thereof, which are capable of improving a low light level characteristic of the CMOS image sensor....
7135361 Method for fabricating transistor gate structures and gate dielectrics thereof  
Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more...
7132322 Method for forming a SiGe or SiGeC gate selectively in a complementary MIS/MOS FET device  
Form a dielectric layer on a semiconductor substrate. Deposit an amorphous Si film or a poly-Si film on the dielectric layer. Then deposit a SiGe amorphous-Ge or polysilicon-Ge thin film theteover....
7132332 Semiconductor memory device and manufacturing method thereof  
A polysilicon film and the like are patterned to form n − diffusion layers on a silicon substrate. Subsequently, an outer edge of an Al 2 O 3 film is made retreat to be smaller than that of a...
7129126 Method and structure for forming strained Si for CMOS devices  
A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate and forming a...
7129551 Electronic component having a praseodymium oxide layer and process for fabricating same  
An electronic component is disclosed having a first layer of metallically conductive material, a second layer of semiconductor material, and a third layer between the first and second layers. The...
7125785 Mixed orientation and mixed material semiconductor-on-insulator wafer  
The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor...
7122417 Methods for fabricating metal-oxide-semiconductor field effect transistors using gate sidewall spacers  
Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is fabricated by forming gate spacers on both sidewalls of a gate pattern in a semiconductor substrate including first and second regions....
7122414 Method to fabricate dual metal CMOS devices  
The present invention relates generally to barrier layers in transistor gate stacks in integrated circuits, and to processes for forming such gate stacks.
7118948 Semiconductor wafer having different impurity concentrations in respective regions  
A semiconductor wafer has different impurity concentrations in respective regions and gate patterns have different lengths in the respective regions. The semiconductor wafer has different impurity...
7118952 Method of making transistor with strained source/drain  
A method of fabricating a transistor comprises the steps of: forming a gate electrode above a substrate made of a first semiconductor material having a first lattice spacing, forming recesses in...
7118972 Method of manufacture of a semiconductor device  
A method of manufacture of a semiconductor device uses simplified steps while improving the electrical properties of each element in the semiconductor device. Over a semiconductor substrate, having...
7119381 Complementary metal-oxide-semiconductor field effect transistor structure having ion implant in only one of the complementary devices  
A complementary metal-oxide-semiconductor field effect transistor structure includes ion implants in only one of the two complementary devices. The transistor structure generally includes a...
7119404 High performance strained channel MOSFETs by coupled stress effects  
Strained channel transistors including a PMOS and NMOS device pair to improve an NMOS device performance without substantially degrading PMOS device performance and method for forming the same, the...
7118953 Process of fabricating termination region for trench MIS device  
A trench MIS device is formed in a semiconductor die that contains a P-epitaxial layer that overlies an N+ substrate and an N-epitaxial layer. In one embodiment, the device includes a drain-drift...
7115924 Pixel with asymmetric transfer gate channel doping  
A pixel including a substrate of a first conductivity type, a photodetector of a second conductivity type that is opposite the first conductivity type and configured to convert incident light to a...
7115954 Semiconductor device including stress inducing films formed over n-channel and p-channel field effect transistors and a method of manufacturing the same  
A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p...
7112480 Method and structure for a low voltage CMOS integrated circuit incorporating higher-voltage devices  
A CMOS integrated circuit ( 15 A-B-C) includes both relatively low-power ( 124, 126 ) and high-power ( 132, 134 ) CMOS transistors on the same chip. A 20V, relatively high-power PMOS device ( 134 )...
7112481 Method for forming self-aligned dual salicide in CMOS technologies  
A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first...
7109078 CMOS compatible process for making a charge trapping device  
A method of making an n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that uses charge trapping for altering channel conductivity characteristics is disclosed. Other...
7109077 Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound  
A dielectric layer ( 50 ) is formed over a semiconductor ( 10 ) that contains a first region ( 20 ) and a second region ( 30 ). A polysilicon layer is formed over the dielectric layer ( 50 ) and...
7109076 Method of manufacturing semiconductor integrated circuit device, and semiconductor integrated circuit device made by its method  
Mutual diffusion of impurities in a gate electrode is suppressed near a boundary between an n-channel type MISFET and a p-channel type MISFET, which adopt a polycide's dual-gate structure. Since a...
7109079 Metal gate transistor CMOS process and method for making  
A method for forming a semiconductor device ( 100 ) includes a semiconductor substrate ( 102 ) having a first region ( 104 ), forming a gate dielectric ( 108 ) over the first region, forming a...
7105390 Nonplanar transistors with metal gate electrodes  
A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate. A gate dielectric is formed on...
7101746 Method to lower work function of gate electrode through Ge implantation  
A method for forming selective P type and N type gates is described. A gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide...
7101744 Method for forming self-aligned, dual silicon nitride liner for CMOS devices  
A method for forming a self-aligned, dual silicon nitride liner for CMOS devices includes forming a first type nitride layer over a first polarity type device and a second polarity type device, and...
7101747 Dual work function metal gates and methods of forming  
Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors can be formed from a metal silicon compound deficient of...
7098095 Method of forming a MOS transistor with a layer of silicon germanium carbon  
The vertical diffusion of dopants from the gate into the channel region, and the lateral diffusion of dopants from the source and drain regions into the channel region resulting from thermal...
7098114 Method for forming cmos device with self-aligned contacts and region formed using salicide process  
A method for forming CMOS devices on a semiconductor substrate is disclosed in which gate structures are formed within both the core region and the non-core region of the semiconductor substrate....
7098094 NiSi metal gate stacks using a boron-trap  
A capping layer ( 118 ) is used during an anneal to form fully silicided NiSi gate electrodes ( 120 ). The capping layer ( 118 ) comprises a material with an affinity for boron, such as TiN. The...
7091079 Method of forming devices having three different operation voltages  
The present invention provides a method of forming devices having different operation voltages. First, a substrate having an HV region, an MV region, and an LV region is provided. Then, at least a...
7087476 Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit  
Complementary metal oxide semiconductor integrated circuits may be formed with NMOS and PMOS transistors having different gate dielectrics. The different gate dielectrics may be formed, for...
7087477 FinFET SRAM cell using low mobility plane for cell stability and method for forming  
The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The...
7084025 Selective oxide trimming to improve metal T-gate transistor  
A process to form a FET using a replacement gate. An example feature is that the PMOS sacrificial gate is made narrower than the NMOS sacrificial gate. The PMOS gate is implanted preferably with Ge...
7084024 Gate electrode forming methods using conductive hard mask  
Methods related to formation of a gate electrode are disclosed that employ a conductive hard mask as a protective layer during a photoresist removal process. In preferred embodiments, the...
7084026 Semiconductor device and method for fabricating the same  
A region of an Si layer 15 located between source and drain regions 19 and 20 is an Si body region 21 which contains an n-type impurity of high concentration. An Si layer 16 and an SiGe...
7081379 Local interconnect for integrated circuit  
An integrated circuit having a gate region, a source drain region, and an electrically nonconductive spacer separating the gate region and the source drain region. A local interconnect electrically...
7074664 Dual metal gate electrode semiconductor fabrication process and structure thereof  
A semiconductor fabrication process includes patterning a first gate electrode layer overlying a gate dielectric. A second gate electrode layer is formed overlying the first gate electrode layer...
7074663 Method of making semiconductor device including a first set of windows in a mask with larger ratio of surface area than a second set of windows  
A method of creating two or more semiconductor elements of different characteristics in one and the same semiconductor substrate. Two antimony-diffused regions are formed in a p-type semiconductor...
7074662 Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage  
A method of forming a fin field effect transistor on a semiconductor substrate includes forming a vertical fin protruding from the substrate. A buffer oxide liner is formed on a top surface and on...
7074660 FinFet device and method of fabrication  
A transistor fin of a fin field-effect transistor is arranged between two contact structures. A gate electrode encapsulating the transistor fin on three sides is caused to recede by means of a...
7067364 Gate structures having sidewall spacers using selective deposition and method of forming the same  
Gate stacks with sidewall spacers having improved profiles to suppress or eliminate void formation between the gate stacks during gap-filling is disclosed, along with a method of forming the gate...
7067365 High-voltage metal-oxide-semiconductor devices and method of making the same  
An improved high-voltage process is disclosed. In order to improve the performance in terms of breakdown voltage and to maintain the integrity of the STI structures, the thick gate oxide layer of...
7067366 Method of making field effect transistors having self-aligned source and drain regions using independently controlled spacer widths  
A method is provided for defining spacings between the gates of field effect transistors (FETs) of an integrated circuit and the source and drain regions thereof, the spacings differing in width...
Matches 351 - 400 out of 930 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >