Matches 651 - 700 out of 927 < 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 >
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6486012 Semiconductor device having field effect transistors different in thickness of gate electrodes and process of fabrication thereof  
An n-channel type field effect transistor and a p-channel type field effect transistor are fabricated on a p-type well and an n-type well, respectively, and the arsenic-doped gate electrode of the...
6486007 Method of fabricating a memory cell for a static random access memory  
A method is disclosed for a memory cell for a static random access memory. The memory cell includes a pair of cross-coupled CMOS logic inverters that are connected together to form a latch, and a...
6479339 Use of a thin nitride spacer in a split gate embedded analog process  
A mixed voltage CMOS process for high reliability and high performance core transistors and input-output and analog transistors with reduced mask steps. A patterned silicon nitride film 160 is...
6479350 Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers  
CMOS semiconductor devices comprising MOS transistors of different channel conductivity type are formed in or on a common semiconductor substrate using a minimum number of critical masks....
6475844 Field effect transistor and method of manufacturing same  
A silicided region ( 11 a ) is formed in part of a surface of a gate electrode ( 3 a ) which is far from a storage node when a diffusion region ( 7 a ) is connected to a bit line and a diffusion...
6472243 Method of forming an integrated CMOS capacitive pressure sensor  
A capacitive pressure sensor ( 10 ) utilizes a diaphragm ( 38 ) that is formed along with forming gates ( 56,57 ) of active devices on the same semiconductor substrate ( 11 ).
6468860 Integrated circuit capable of operating at two different power supply voltages  
A method for manufacturing an integrated circuit having high voltage transistors and low voltage transistors is disclosed. First, lightly doped drains are formed in both high voltage transistors...
6468848 Method of fabricating electrically isolated double gated transistor  
A gated field effect transistor (gated-FET) in which the body of the FET is electrically isolated from the substrate thereby reducing leakage current through parasitic bipolar action. The back-bias...
6465295 Method of fabricating a semiconductor device  
A semiconductor device fabrication method comprises the steps of forming a gate insulating film on a surface of a semiconductor substrate, forming a polysilicon film on the gate insulating film,...
6465283 Structure and fabrication method using latch-up implantation for improving latch-up immunity in CMOS fabrication process  
A structure and fabrication method using latch-up implantation to improve latch-up immunity in CMOS circuit. The impedance of parasitic SCR conducting path is raised by performing an...
6455895 Overvoltage protector having same gate thickness as the protected integrated circuit  
A semiconductor integrated circuit having an input protection device which is suitable for receiving inputs of signals having voltages higher than the internal power supply voltage is provided. The...
6451657 Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant  
A process is disclosed for fabricating a transistor having a channel length that is smaller than lengths resolvable using common photolithography techniques. A gate oxide layer is formed over a...
6451656 CMOS inverter configured from double gate MOSFET and method of fabricating same  
A method of forming a semiconductor line from a semiconductor-on-insulator (SOI) wafer, the SOI wafer having a substrate with a buried oxide (BOX) layer disposed thereon and a semiconductor active...
6451640 Semiconductor device having NMOS and PMOS transistors on common substrate and method of fabricating the same  
There is provided a method of fabricating a semiconductor device, including the steps of (a) forming first well regions in a semiconductor substrate in all regions in which high-voltage and...
6448122 Method and device structure for enhanced ESD performance  
An integrated circuit manufacturing process selectively blocks silicide formation during the fabrication of I/O devices to enhance their ESD performance while not impacting the performance of core...
6444523 Method for fabricating a memory device with a floating gate  
A fabrication method for a memory device with a floating gate is provided. A substrate is provided. A channel doping step is performed on the substrate, wherein the actual threshold voltage of the...
6440802 Process for fabricating semiconductor device and photolithography mask  
A process for fabricating a semiconductor device including MOS transistors of low breakdown voltage type and of high breakdown voltage type provided on a semiconductor substrate, the MOS transistor...
6436748 Method for fabricating CMOS transistors having matching characteristics and apparatus formed thereby  
A method for forming NMOS and PMOS transistors that includes cutting a substrate along a (111) orientation and fabricating deep sub-micron NMOS and PMOS transistors thereon. The complementary NMOS...
6436749 Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion  
A method for forming mixed high voltage/low voltage (HV/LV) transistors for CMOS devices is disclosed. In an exemplary embodiment, depletion of the gate conductor is controlled by leaving a fixed...
6432759 Method of forming source and drain regions for CMOS devices  
Method for producing an NMOS, PMOS or CMOS semiconductor device with reduced substrate current and increased device lifetime. A source-gate-drain device is fabricated having a moderately doped...
6429080 Multi-level dram trench store utilizing two capacitors and two plates  
A multi-level memory cell capable of storing two or three bits of digital data occupies only four lithographic squares and requires only one or two logic level voltage sources, respectively. High...
6429062 Integrated-circuit manufacturing using high interstitial-recombination-rate blocking layer for source/drain extension implant  
In the fabrication of a 0.10 micron CMOS integrated circuit, a high-energy plasma etch is used to pattern a polysilicon layer and an underlying gate oxide layer to define gate structures. A thermal...
6420221 Method of manufacturing a highly latchup-immune CMOS I/O structure  
CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion...
6417074 Method of manufacturing a structure for reducing leakage currents by providing isolation between adjacent regions of an integrated circuit  
A fabrication method for providing isolation between adjacent regions of an integrated circuit includes providing a guard layer over field edges that are the interfaces between field oxide regions...
6417037 Method of dual gate process  
A new method for forming dual gate dielectrics having high quality where both thin and thick gate dielectric thicknesses can be controlled separately is described. An isolation region separates a...
6413811 Method of forming a shared contact in a semiconductor device including MOSFETS  
An objective of this invention is to provide a process for manufacturing a shared contact without protrusion toward an adjacent gate electrode and an improved shared contact. This invention allows...
6413808 Semiconductor device and process for production thereof  
In the semiconductor device disclosed in the present invention, the well regions in the internal circuit comprise high-impurity-concentration regions 4 and 5 as lower layers and...
6410376 Method to fabricate dual-metal CMOS transistors for sub-0.1 &mgr m ULSI integration  
A new method for forming a dual-metal gate CMOS transistors is described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A nitride layer is...
6410375 Methods of forming transistors including gate dielectric layers having different nitrogen concentrations  
A method of forming an electronic device on a semiconductor substrate includes forming first and second field effect transistors on a substrate. In particular, the first field effect transistor...
6406954 Method for forming out-diffusing a dopant from the doped polysilicon into the N-type and P-type doped portion  
In one aspect, the invention includes a semiconductor processing method of diffusing dopant into both n-type and p-type doped regions of a semiconductive substrate. A semiconductive material is...
6406952 Process for device fabrication  
A process for device fabrication, comprising the steps of forming a dielectric material region on a silicon substrate, forming a first amorphous silicon or polysilicon region on the dielectric...
6406955 Method for manufacturing CMOS devices having transistors with mutually different punch-through voltage characteristics  
A CMOS device which includes first and second wells formed in first and second regions of a semiconductor substrate, respectively, first and second transistors formed in the respective wells, a...
6395644 Process for fabricating a semiconductor device using a silicon-rich silicon nitride ARC  
A process for fabricating a semiconductor device using an ARC layer includes the formation of a silicon-rich silicon nitride material to provide an anti-reflective layer over a electrically...
6395591 Selective substrate implant process for decoupling analog and digital grounds  
An integrated circuit fabrication process includes a selective substrate implant process to effectively decouple a first power supply connection from a second power supply connection while...
6391698 Forming complementary metal-oxide semiconductor with gradient doped source/drain  
The present invention provides a method for forming a transistor with a gradient doped source/drain. The method comprises the following steps. First, two first N-wells are formed in a substrate and...
6387743 Semiconductor device manufacturing method and semiconductor device  
A semiconductor device and manufacturing method capable of forming shallow extension regions in insulated-gate transistors. A side wall material containing about 1 to 20% of phosphorus, such as...
6388288 Integrating dual supply voltages using a single extra mask level  
Integration of dual voltages on a single chip can be accomplished with a minimum of extra masks by optimizing only the MDD implant of the peripheral transistors, while other implants remain the...
6380013 Method for forming semiconductor device having epitaxial channel layer using laser treatment  
A method for fabricating a semiconductor device, and, more particularly, a method for fabricating a transistor using an epitaxial channel and a laser thermal treatment is disclosed. The method for...
6380015 MOSFETs with improved short channel effects and method of making the same  
In the manufacture of CMOS devices, the n+ gate is partially counterdoped with boron to produce a modified p-type FET that has improved short channel effects, reduced gate induced drain leakage and...
6380021 Ultra-shallow junction formation by novel process sequence for PMOSFET  
A new method for forming ultra-shallow junctions for PMOSFET while reducing short channel effects is described. A semiconductor substrate wafer is provided wherein there is at least one NMOS active...
6376296 High-voltage device and method for manufacturing high-voltage device  
A high-voltage device. A substrate has a first conductive type. A first well region with the first conductive type is located in the substrate. A second well region with the second conductive type...
6376293 Shallow drain extenders for CMOS transistors using replacement gate design  
A method of fabricating a CMOS transistor to construct shallow drain extenders ( 30 ) using a replacement gate design. The method involves forming epitaxial layers ( 30 ) and ( 220 ) the will later...
6372569 Selective formation of hydrogen rich PECVD silicon nitride for improved NMOS transistor performance  
A method of selective formation of SiN layer in a semiconductor device comprising the following steps. A semiconductor structure having at least one PMOS transistor and one NMOS transistor formed...
6368952 Diffusion inhibited dielectric structure for diffusion enhanced conductor layer  
Within a method for forming a microelectronic fabrication, there is first provided a substrate. There is then formed over the substrate a microelectronic device passivated with a patterned first...
6365426 Method of determining the impact of plasma-charging damage on yield and reliability in submicron integrated circuits  
The present invention provides a method of determining a reliability of a semiconductor device. In an exemplary embodiment, the method determines an oxide stress voltage as a function of an antenna...
6362035 Channel stop ion implantation method for CMOS integrated circuits  
A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field...
6362034 Method of forming MOSFET gate electrodes having reduced depletion region growth sensitivity to applied electric field  
A method of fabricating a FET having a gate electrode with reduced susceptibility to the carrier depletion effect, includes increasing the amount of n-type dopant in the gate electrode of an...
6362059 Production of a semiconductor device having a P-well  
A process for preparing a semiconductor which is capable of implanting indium effectively during the process of forming a gate insulation film with different levels of thickness includes a 1 st ...
6358824 Integrated circuits with tub-ties and shallow trench isolation  
A method of fabricating an IC comprises the steps of: (a) forming trench isolation regions in a surface of a semiconductor body; and (b) forming a tub-tie region between at least one pair of the...
6352913 Damascene process for MOSFET fabrication  
An improved MOSFET transistor is disclosed having a high dielectric constant gate dielectric and a metal gate electrode. With such a procedure, the known problems with polysilicon gate electrodes...
Matches 651 - 700 out of 927 < 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 >