Matches 601 - 650 out of 932 < 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 >
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6627502 Method for forming high concentration shallow junctions for short channel MOSFETs  
A method is taught for forming shallow LDD diffusions using polysilicon sidewalls as a diffusion source. The polysilicon sidewalls are formed along side squared-off silicon nitride sidewall spacers...
6627475 Buried photodiode structure for CMOS image sensor  
A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provided, containing a p-type region. An n-type photodiode region is formed within the p-type region....
6627489 Method of producing CMOS transistors and related devices  
A method for making CMOQ transistors and associated devices. The method is used to make transistors of a first type and a second type in CMOS technology in an active layer. The method etches...
6624032 Structure and process flow for fabrication of dual gate floating body integrated MOS transistors  
A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer...
6624043 Metal gate CMOS and method of manufacturing the same  
A metal gate complementary metal oxide semiconductor (CMOS) and a method of manufacturing the same is disclosed. The method includes depositing the metal gate electrode material as a final step...
6624014 Process for fabricating a deep submicron complementary metal oxide semiconductor device having ultra shallow junctions  
A process for fabricating a deep submicron complementary metal oxide semiconductor device having ultra shallow junctions. After a gate is formed on the substrate on which an N well region and a P...
6620668 Method of fabricating MOS transistor having shallow source/drain junction regions  
A method of fabricating a MOS transistor having shallow source/drain junction regions is provided. A diffusion source layer is formed on a semiconductor substrate on which gate patterns are formed....
6613624 Method for fabricating an integrated semiconductor circuit  
Integrated semiconductor circuits have MOS transistors whose gate electrodes are provided with dopings in order to set the electrical potential of the channel region by an altered work function of...
6614078 Highly latchup-immune CMOS I/O structures  
CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion...
6613622 Method of forming a semiconductor device and structure therefor  
A semiconductor device ( 10, 40 ) is formed to have a well ( 19 ) in a substrate ( 11 ). The well and the substrate have the same doping type, for example both P-type or both N-type. Low resistance...
6613626 Method of forming CMOS transistor having a deep sub-micron mid-gap metal gate  
A CMOS transistor is formed on a single crystal silicon substrate. Active regions are formed on the substrate, including an nMOST active region and a pMOST active region. An epitaxial layer of...
6613635 Method of fabricating semiconductor device having element isolation trench  
Threshold voltage fluctuation in upper corner portions of a trench isolation is inhibited by rounding upper corner portions of the trench by thermal oxidation, introducing a first impurity into...
6610181 Method of controlling the formation of metal layers  
The present invention is directed to a method of controlling the formation of metal layers. In one illustrative embodiment, the method comprises depositing a layer of metal above a structure,...
6608365 Low leakage PMOS on-chip decoupling capacitor cells compatible with standard CMOS cells  
An on-chip decoupling capacitor cell is disclosed that is compatible with standard CMOS cells. A cell boundary defining the area of the cell includes a first transistor area and a second transistor...
6605499 Method of forming sea-of-cells array of transistors  
The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is...
6593628 Semiconductor device and method of manufacturing same  
The invention relates to an essentially discrete semiconductor device comprising a semiconductor body ( 10 ) having a first, preferably bipolar, transistor (T 1 ) with a first region ( 1 ) forming...
6586331 Low sheet resistance of titanium salicide process  
A method for establishing low sheet resistance for the Titanium Salicide process that teaches a C-54 TiSi x process by means of an additional vacuum bake. The present invention teaches an...
6586289 Anti-spacer structure for improved gate activation  
A method and structure for improving the gate activation of metal oxide semiconductor field effect transistor (MOSFET) structures are provided. The method of the present invention includes the...
6583012 Semiconductor devices utilizing differently composed metal-based in-laid gate electrodes  
MOS transistor and CMOS devices comprising a plurality of transistors including in-laid, metal-based gate electrodes of different composition are formed by a process comprising: depositing a first...
6581028 Profile extraction method and profile extraction apparatus  
In a profile extraction method, a long channel profile is first extracted through an initial profile generating stage and a long channel profile extraction stage. In a following two-dimensional...
6573133 Method of forming spacers in CMOS devices  
A sidewall spacer is formed in a CMOS device by depositing a layer of silicon nitride on a wafer and anisotropically etching away the silicon nitride layer with a chorine-based plasma etchant.
6569784 Material of photoresist protect oxide  
A new layer of RPO is provided for semiconductor devices, specifically for semiconductor device having sub-micron device feature size. The layer of RPO that is provided by the invention comprises a...
6570228 Method and apparatus for electrically measuring insulating film thickness  
A method and an apparatus for measuring insulating film thickness, such as the width of sidewall spacers. The method includes positioning a first test structure having a first resistance at a first...
6569715 Large grain single crystal vertical thin film polysilicon mosfets  
A vertical thin film transistor formed in a single grain of polysilicon having few or no grain boundaries for use in memory, logic and display applications. The transistor is formed from a thin...
6566203 Method for preventing electron secondary injection in a pocket implantation process  
A method for preventing electron secondary injection in a pocket implantation process performed on a nitride read only memory (NROM). The NROM has an oxide-nitride-oxide (ONO) layer formed on a...
6566181 Process for the fabrication of dual gate structures for CMOS devices  
In accordance with the invention, a process for forming a dual gate structure for CMOS devices comprises the steps of a) providing a semiconductor workpiece including n-type and p-type regions and...
6566204 Use of mask shadowing and angled implantation in fabricating asymmetrical field-effect transistors  
To furnish an IGFET ( 120 or 122 ) with an asymmetrically doped channel zone ( 144 or 164 ), a mask ( 212 ) is provided over a semiconductor body and an overlying electrically insulated gate...
6559051 Electroless deposition of dielectric precursor materials for use in in-laid gate MOS transistors  
High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in...
6555357 FEN-1 endonuclease, mixtures and cleavage methods  
The present invention relates to means for the detection and characterization of nucleic acid sequences, as well as variations in nucleic acid sequences. The present invention also relates to...
6551883 MOS device with dual gate insulators and method of forming the same  
A MOS device with dual gate insulators has a first gate insulator formed on a predetermined area of a semiconductor substrate, and a second gate insulator formed outside the predetermined area of...
6545317 Semiconductor device having a gate electrode with a sidewall insulating film and manufacturing method thereof  
A gate electrode is provided via a gate insulating film formed between the source and drain regions on a semiconductor substrate, wherein the sidewall of the gate electrode excluding the exposed...
6541322 Method for preventing gate depletion effects of MOS transistor  
The present invention shows a method of fabricating a MOS transistor on the substrate of a semiconductor wafer and of preventing the gate depletion effects occurring in the MOS transistor. The...
6541320 Method to controllably form notched polysilicon gate structures  
A method and structure for forming a notched gate structure having a gate conductor layer on a gate dielectric layer. The gate conductor layer has a first thickness. The inventive method includes...
6534335 Optimized low leakage diodes, including photodiodes  
A photodiode for use in an imager having an improved charge leakage. The photodiode has a doped region that is spaced away from the field isolation to minimize charge leakage. A second embodiment...
6534354 Method of manufacturing MOS transistor with fluorine implantation at a low energy  
A method of manufacturing a MOS transistor. A substrate having a gate oxide layer, a gate electrode and spacers attached to the sidewalls of the gate electrode is provided. A source/drain (S/D)...
6531351 Method for forming a CMOS circuit of GaAS/Ge on Si substrate  
A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high...
6528401 Method for fabricating polycide dual gate in semiconductor device  
Method for fabricating a polycide dual gate in a semiconductor device fabricates a dual gate having polycide gate electrodes. The polycide can be a cobalt polycide, for example. The method can...
6528362 Metal gate with CVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process  
A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited...
6524902 Method of manufacturing CMOS semiconductor device  
In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor...
6524904 Method of fabricating semiconductor device  
After P + ions are implanted into a polysilicon film in an nMOSFET region, a heat treatment is performed to diffuse phosphorus down to the lower part of the polysilicon film. The diffusion reduces...
6521493 Semiconductor device with STI sidewall implant  
A semiconductor device and method of manufacturing the same are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. After...
6518178 Method for forming a field effect transistor having increased breakdown voltage  
A method of fabricating bipolar junction transistors particularly suitable for electrostatic discharge protection and high voltage MOSFETs. In accordance with the invention, a mask covers bird's...
6518154 Method of forming semiconductor devices with differently composed metal-based gate electrodes  
MOS transistors and CMOS devices comprising a plurality of transistors including metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket...
6514839 ESD implantation method in deep-submicron CMOS technology for high-voltage-tolerant applications with light-doping concentrations  
An implanting method forms high-voltage-tolerant ESD protection devices (ESDPD) for deep-submicron CMOS process activated between LDD implanting and forming sidewall spacers. ESD-Implant (ESDI)...
6514833 Method of inhibiting lateral diffusion between adjacent wells by introducing carbon or fluorine ions into bottom of STI groove  
Semiconductor devices comprising a plurality of active device regions formed in a common semiconductor substrate, e.g., CMOS devices, are formed by utilizing shallow trench isolation (STI)...
6512273 Method and structure for improving hot carrier immunity for devices with very shallow junctions  
An integrated circuit CMOS structure and method for forming the structure provides gate sidewall spacers which are independently optimized for the n-channel and p-channel devices to improve...
6509221 Method for forming high performance CMOS devices with elevated sidewall spacers  
A method is described for making elevated sidewall spacers on the gate structure of a semiconductor device. A first insulating layer is deposited on the substrate, so that an upper portion of each...
6506619 Structure of a CMOS image sensor and method for fabricating the same  
A method of fabricating CMOS image sensor. On a substrate, an isolation layer is formed to partition the substrate into a photodiode sensing region and a transistor element region. Next, on the...
6503788 Semiconductor device and method of manufacture thereof  
In order to realize a dual gate CMOS semiconductor device with little leakage of boron that makes it possible to divisionally doping a p-type impurity and an n-type impurity into a polycrystalline...
6503784 Double gated transistor  
A semiconductor body-having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being...
Matches 601 - 650 out of 932 < 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 >