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Match Document Document Title
6770520 Floating gate and method of fabricating the same  
A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which a gate dielectric layer, a conducting layer, and a patterned hard mask layer are sequentially formed....
6770522 Semiconductor device and manufacturing method thereof  
A semiconductor device and a manufacturing method thereof which is suited for forming both a transistor for a memory cell and a transistor for a high voltage circuit part on one semiconductor...
6770521 Method of making multiple work function gates by implanting metals with metallic alloying additives  
A method of forming a first and second transistors with differing work function gates by differing metals with a second metal selectively implanted or diffused into a first metal.
6764890 Method of adjusting the threshold voltage of a mosfet  
In one embodiment, the threshold voltage of a first transistor is adjusted by implanting a dopant through a mask (e.g., photoresist material). The thickness of the mask may be varied to obtain a...
6762101 Damascene double-gate FET  
A double-gate field effect transistor (DGFET) is provided using a damascene-like replacement gate processing step to create sidewall source/drain regions, oxide spacers and gate structures inside a...
6762085 Method of forming a high performance and low cost CMOS device  
A method of fabricating a CMOS device with reduced processing costs as a result of a reduction in photolithographic masking procedures, has been developed. The method features formation of L shaped...
6753239 Bond and back side etchback transistor fabrication process  
A supporting structure is wafer-bonded to the upper face side of a partially or fully processed device wafer. The device wafer includes a transistor having a well region that extends into the...
6753216 Multiple gate transistor employing monocrystalline silicon walls  
A semiconductor fabrication process and structure in which a dielectric structure ( 106 ) is formed upon a substrate ( 102 ). Silicon is then deposited and processed to form a crystalline silicon...
6746906 Transistor with ultra-short gate feature and method of fabricating the same  
In one embodiment of the present invention, a method of forming semiconductor transistors includes: forming a gate electrode over but insulated from a semiconductor body region; forming off-set...
6746943 Semiconductor device and method of fabricating the same  
A semiconductor device has a semiconductor substrate, a first transistor having a first gate electrode formed of a polycrystalline silicon germanium film as formed above said semiconductor...
6740550 Methods of manufacturing semiconductor devices having chamfered silicide layers therein  
A semiconductor device having a chamfered silicide layer and a manufacturing method of the same. The semiconductor device includes: a first insulation layer overlying a semiconductor substrate;...
6740551 Method of manufacturing a semiconductor integrated circuit  
A semiconductor integrated circuit is provided in which a change in timing of a circuit or variation in a driving ability do not occur even if the potential of a support substrate is fixed. The...
6740549 Gate structures having sidewall spacers using selective deposition and method of forming the same  
Gate stacks with sidewall spacers having improved profiles to suppress or eliminate void formation between the gate stacks during gap-filling is disclosed, along with a method of forming the gate...
6737309 Complementary MISFET  
A gate electrode of an n-type MIS transistor includes a first metal-containing film, which is formed in contact with a gate insulation film and has a Fermi level on a conductive band side from a...
6737354 Method of CMOS source/drain extension with the PMOS implant spaced by poly oxide and cap oxide from the gates  
An improved source/drain extension process is provided by processing steps (steps A and G) that cover the wafer and dry etching steps (steps D and I) that provide side wall spacers of poly oxide...
6734496 Semiconductor device  
A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a...
6735072 On-chip decoupling capacitors designed for a 0.11 micron and beyond dual gate oxide CMOS technology  
A decoupling capacitor suitable for use with 0.11 micron or less, for example 0.09 micron, CMOS technology is provided herein. The decoupling capacitor includes a decoupling structure that...
6727135 All-in-one disposable/permanent spacer elevated source/drain, self-aligned silicide CMOS  
A complementary metal oxide semiconductor (CMOS) device having silicide contacts that are self-aligned to deep junction edges formed within a surface of a semiconductor substrate as well as a...
6727130 Method of forming a CMOS type semiconductor device having dual gates  
A method of forming a CMOS type semiconductor device having dual gate includes forming a first gate insulation layer and a first metal-containing layer sequentially on a surface of a substrate in...
6727131 System and method for addressing junction capacitances in semiconductor devices  
A method of forming a semiconductor device is provided that comprises forming a gate conductor proximate to and insulated from an outer surface of a semiconductor substrate. The gate conductor...
6723593 Deep submicron MOS transistor with increased threshold voltage  
A deep submicron MOS transistor is formed with multiple control gates by forming side wall control gates adjacent to the gate oxide spacers over heavily-doped regions of the source and drain...
6713334 Fabricating dual voltage CMOSFETs using additional implant into core at high voltage mask  
An implant at HVGX pattern (step 102 c ) is provided to allow selective transistor threshold voltage Vth adjustment on the core transistors without affecting the I/O transistor threshold voltage...
6713335 Method of self-aligning a damascene gate structure to isolation regions  
A process for fabricating a CMOS device in which conductive gate structures are defined self-aligned to shallow trench isolation (STI), regions, without using a photolithographic procedure, has...
6709912 Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimization  
A method for forming a dual Si—Ge poly-gates having different Ge concentrations is described. An NMOS active area and a PMOS active area are provided on a semiconductor substrate separated by an...
6706603 Method of forming a semiconductor device  
The present invention provides a method of forming a vertical replacement gate (VRG) device on a semiconductor substrate. The method includes depositing an epitaxial layer over a first source/drain...
6706577 Formation of dual gate oxide by two-step wet oxidation  
A method of simultaneously forming differential gate oxide for both high and low voltage transistors using a two-step wet oxidation process is described. A semiconductor substrate is provided...
6703269 Method to form gate conductor structures of dual doped polysilicon  
A method for manufacturing a semiconductor chip which has transistors is disclosed. The transistors include first type transistors which have a first type of doping and second type transistors...
6699776 MOSFET gate insulating film and method of manufacturing the same  
A semiconductor device where an interface circuit operating on a high power supply voltage and exchanging signals and data with an external device and an internal circuit operating on a low power...
6699744 Method of forming a MOS transistor of a semiconductor device  
The disclosure relates to a method of forming a MOS transistor of a semiconductor device and, more particularly, to a method of forming a PMOS transistor of a semiconductor device that minimizes...
6696328 CMOS gate electrode using selective growth and a fabrication method thereof  
A CMOS gate electrode formed using a selective growth method and a fabrication method thereof, wherein, in the CMOS gate electrode, a first gate pattern of polysilicon germanium (poly-SiGe) is...
6693001 Process for producing semiconductor integrated circuit device  
A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a...
6686233 Integration of high voltage self-aligned MOS components  
The invention relates to a method for forming a high voltage NMOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, in an n-well CMOS process...
6682965 Method of forming n-and p- channel field effect transistors on the same silicon layer having a strain effect  
A method for forming a Field Effect Transistor (FET) within a strain effect semiconductor layer is disclosed, whereby the source and drain of the FET are formed only in the strain effect silicon...
6682966 Semiconductor device and method for producing the same  
A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type...
6680225 Method for manufacturing a semiconductor memory  
The method for manufacturing a Semiconductor Memory according to the present invention comprises a step for forming a gate insulator film on the surface of a semiconductor substrate; a step for...
6677194 Method of manufacturing a semiconductor integrated circuit device  
A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS,...
6670201 Manufacturing method of semiconductor device  
A manufacturing method of a semiconductor device capable of obtaining highly reliable semiconductor devices with the realization of high integration and high speed intended is provided. During...
6670226 Planarizing method for fabricating gate electrodes  
Within a method for fabricating a semiconductor integrated circuit microelectronic fabrication, there is employed a planarizing method for forming, in a self aligned fashion, a patterned second...
6667200 Method for forming transistor of semiconductor device  
A method for forming a transistor of a semiconductor device, including the step of forming channel layers of a first and a second conductive types, performing high temperature thermal process to...
6661063 Semiconductor integrated circuit device  
Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs...
6660578 High-K dielectric having barrier layer for P-doped devices and method of fabrication  
A semiconductor device, a semiconductor wafer and a method of forming a semiconductor wafer where a barrier layer is used to inhibit P-type ion-penetration into a dielectric layer made from a...
6660577 Method for fabricating metal gates in deep sub-micron devices  
A method for fabricating metal gates in deep sub-micron CMOS devices. The method blanket deposits a transition metal nitride layer on top of a gate dielectric layer for forming gate electrodes for...
6660602 Stand-alone triggering structure for ESD protection of high voltage CMOS  
In a stand-alone snapback NMOS ESD protection structure method of manufacturing, the breakdown voltage is reduced and the structure is made more resilient to hot carrier and soft leakage...
6653180 Transistors including gate dielectric layers having different nitrogen concentrations and related structures  
An electronic device on a semiconductor substrate can include first and second field effect transistors on a substrate. In particular, the first field effect transistor includes a first gate...
6649457 Method for SOI device isolation  
A method of isolating a CMOS device on a silicon on insulator substrate, wherein the substrate includes an insulating layer of top silicon formed thereon, includes growing a gate oxide layer on the...
6645818 Method to fabricate dual-metal gate for N- and P-FETs  
A new method for forming a dual-metal gate CMOS transistors is described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A nitride layer is...
6635522 Method of forming a MOS transistor in a semiconductor device and a MOS transistor fabricated thereby  
Methods of forming a MOS transistor and a MOS transistor fabricated thereby are provided. The MOS transistor includes a semiconductor substrate of a first conductivity type, and an insulated gate...
6635521 CMOS-type semiconductor device and method of fabricating the same  
In the fabrication of a CMOS-TFT, non-selectively doping (for both of p- and n-type TFTS) and selectively doping (only for the n-type TFT) with p-type impurities (B: boron) are successively...
6627502 Method for forming high concentration shallow junctions for short channel MOSFETs  
A method is taught for forming shallow LDD diffusions using polysilicon sidewalls as a diffusion source. The polysilicon sidewalls are formed along side squared-off silicon nitride sidewall spacers...
6627475 Buried photodiode structure for CMOS image sensor  
A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provided, containing a p-type region. An n-type photodiode region is formed within the p-type region....
Matches 551 - 600 out of 930 < 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 >