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9041209 Method and apparatus to improve reliability of vias  
In a disclosed embodiment, a method for tiling selected vias in a semiconductor device having a plurality of vias comprises generating a layout database for the semiconductor device; creating...
9040317 Methods for achieving width control in etching processes  
A method includes performing a patterning step on a layer using a process gas. When the patterning step is performed, a signal strength is monitored, wherein the signal strength is from an...
9034668 Device and method for forming on a nanowire made of a semiconductor an alloy of this semiconductor with a metal or a metalloid  
Device for forming, on a nanowire made of a semiconductor, an alloy of this semiconductor with a metal or metalloid by bringing this nanowire into contact with electrically conductive metal or...
9034666 Method of testing of MEMS devices on a wafer level  
Some embodiments provide methods, process, systems and apparatus for use in testing multi-axis Micro Electro Mechanical Systems (MEMS) devices. In some embodiments, methods of testing are...
9035306 Adjusting configuration of a multiple gate transistor by controlling individual fins  
In a sophisticated semiconductor device, FINFET elements may be provided with individually accessible semiconductor fins which may be connected to a controllable interconnect structure for...
9029173 Method for fabrication of a semiconductor device and structure  
A method for formation of a semiconductor device, the method including: providing a first mono-crystalline layer including first transistors and first alignment marks; providing an interconnection...
9023677 Method for producing spot size converter  
A method for producing a spot size converter includes the steps of forming a first insulator mask on a stacked semiconductor layer; forming first and second terraces, and a waveguide mesa disposed...
9012246 Manufacturing method of semiconductor device and polishing apparatus  
According to an embodiment, a method of manufacturing a semiconductor device includes forming a wiring groove on an insulating film; forming a barrier metal layer and a metal layer; polishing the...
9006739 Semiconductor test and monitoring structure to detect boundaries of safe effective modulus  
A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor...
9006028 Methods for forming ceramic substrates with via studs  
This document describes the fabrication and use of multilayer ceramic substrates, having one or more levels of internal thick film metal conductor patterns, wherein any or all of the metal vias...
9006003 Method of detecting bitmap failure associated with physical coordinate  
A method of detecting bitmap failure associated with physical coordinates is provided. In the method, data of wafer mapping inspection are obtained first, and the data include images of defects in...
8993354 Evaluation pattern, method for manufacturing semiconductor device, and semiconductor wafer  
According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes heating a resistor pattern by scanning the resistor pattern with a first beam. The...
8987012 Method of testing a semiconductor package  
A method of testing a semiconductor package is provided, including: disposing at least an interposer on a top surface of an adhesive layer, the interposer having a first surface and a second...
8987013 Method of inspecting misalignment of polysilicon gate  
A method of inspecting misalignment of a polysilicon gate is disclosed, characterized in forming only NMOS devices in P-wells in a test wafer and utilizing an advanced electron beam inspection...
8987011 Method for determining the structure of a transistor  
A method for determining the structure of a transistor having at least one first layer including GaN, one second layer including AlxGa1-xN disposed on the first layer, and one fourth layer...
8987010 Microprocessor image correction and method for the detection of potential defects  
Systems and methods are provided for developing usable chip images in order to detect and screen defects or anomalies in a manufacturing environment. More specifically, a method is provided for...
8980653 Combinatorial optimization of interlayer parameters  
The embodiments describe methods and apparatuses for combinatorial optimization of interlayer parameters for capacitor stacks. The capacitor stacks may include a substrate, an insulating layer...
8980654 Ion implantation method and ion implantation apparatus  
The ion implantation method includes setting an ion beam scanning speed and a mechanical scanning speed of an object during ion implantation using hybrid scan in advance and implanting ions based...
8975096 Jig, manufacturing method thereof, and flip chip bonding method for chips of ultrasound probe using jig  
A jig includes a wafer including an accommodation groove configured to accommodate a capacitive micromachined ultrasonic transducer (cMUT) when flip chip bonding is performed, and a separation...
8969104 Circuit technique to electrically characterize block mask shifts  
A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask...
8962354 Methods for forming templated materials  
Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on...
8962353 System and methods for semiconductor device performance prediction during processing  
Methods and systems for predicting semiconductor device performance criteria during processing. A method is described that includes receiving a semiconductor wafer; performing semiconductor...
8951813 Method of polishing a substrate having a film on a surface of the substrate for semiconductor manufacturing  
A method of polishing a substrate having a film is provided. The method includes: performing polishing of the substrate in a polishing section; transporting the polished substrate to a wet-type...
8945953 Method of manufacturing semiconductor device  
Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state...
8940554 Method of creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness  
A method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness includes: measuring a thickness of a semiconductor-on-insulator (SOI) layer at a...
8941108 Method to perform electrical testing and assembly of electronic devices  
A method performs electrical testing and assembly of an electronic device on a wafer and comprising a pad made in an oxide layer covered by a passivation layer. The method includes connecting the...
8940558 Techniques for quantifying fin-thickness variation in FINFET technology  
Techniques for quantifying ΔDfin in FINFET technology are provided. In one aspect, a method for quantifying ΔDfin between a pair of long channel FINFET devices includes the steps of: (a) obtaining...
8936949 Solar cell and manufacturing method thereof  
A manufacturing method of a solar cell in which a light receiving side electrode including grid electrodes is provided on one side of a semiconductor substrate, comprises: a first step of forming...
8937310 Detection method for semiconductor integrated circuit device, and semiconductor integrated circuit device  
Integrated circuit layers to be stacked on top of each other are formed with a plurality of inspection rectifier device units, respectively. The inspection rectifier device units including...
8937487 Correction for stress induced leakage current in dielectric reliability evaluations  
Methods, apparatus, and computer program products for evaluating current transients measured during an electrical stress evaluation of a dielectric layer in a semiconductor device. Measured...
8932884 Process environment variation evaluation  
Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures...
8921158 Semiconductor device having mode of operation defined by inner bump assembly connection  
Semiconductor devices are described that are configured to have a state of operation defined by a connection between at least one inner bump assembly and a selected outer bump assembly. In an...
8921127 Semiconductor device and method of simultaneous testing of multiple interconnects for electro-migration  
A semiconductor device has a substrate and conductive layer over the substrate. A resistive element is formed between first and second portions of the conductive layer. A plurality of...
8916393 Method for estimating the diffusion length of metallic species within a three-dimensional integrated structure, and corresponding three-dimensional integrated structure  
A three-dimensional integrated structure may include two assembled integrated circuits respectively including two metallic lines, and at least two cavities passing through one of the integrated...
8912014 Controlling the latchup effect  
A method includes varying spacing between at least one of a source region or a drain region and a well contact region to create a group of configurations. The method further includes determining...
8912049 PEC biasing technique for LEDs  
Each LED in an array of LEDs mounted on a submount wafer has at least a first semiconductor layer exposed and connected to a first electrode of each LED. The submount wafer has a first metal...
8912016 Manufacturing method and test method of semiconductor device  
Provided is a test method by which a transistor whose reliability is low can be detected with low stress and high accuracy in a shorter period of time than a BT test. Provided is to detect a...
8906728 Method for manufacturing a photodetector having a bandwidth tuned honeycomb cell photodiode structure  
A photodetector with a bandwidth-tuned cell structure is provided. The photodetector is fabricated from a semiconductor substrate that is heavily doped with a first dopant. A plurality of...
8906710 Monitor test key of epi profile  
A method and apparatus for estimating a height of an epitaxially grown semiconductor material in other semiconductor devices. The method includes epitaxially growing first, second, and third...
8907490 Semiconductor packages having the first and second chip inclined sidewalls contact with each other  
Semiconductor packages are provided. The semiconductor package includes a first chip having a first inclined sidewall in an edge of the first chip; and a second chip having a second inclined...
8895327 Tipless transistors, short-tip transistors, and methods and circuits therefor  
An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron; and at least one tipless transistor formed in the...
8889526 Apparatus for thinning, testing and singulating a semiconductor wafer  
A wafer translator is provided with a patterned layer of wafer bonding thermoset plastic and is removably attached with a wafer so as to form a wafer/wafer translator pair. The wafer translator...
8883521 Control method of multi-chip package memory device  
A control method of a multi-chip package memory device includes the steps of applying stack signals to stack pads of memory dies, applying a repair signal to repair pads of the respective memory...
8877525 Low cost secure chip identification  
Mechanisms are provided for chip (e.g., semiconductor chip) identification (e.g., low cost secure identification). In one example, a method of manufacturing for implementing integrated chip...
8878183 Method and apparatus for monitoring semiconductor fabrication  
A semiconductor chip for process monitoring of semiconductor fabrication, has a plurality of arrays with a plurality of diodes, each diode being formed in the chip, each diode being associated...
8878182 Probe pad design for 3DIC package yield analysis  
An interposer includes a first surface on a first side of the interposer and a second surface on a second side of the interposer, wherein the first and the second sides are opposite sides. A first...
8878561 Screening method, screening device and program  
This invention is to detect defective products of semiconductor devices with high accuracy even when the characteristics of the semiconductor devices vary according to their positions on each of...
8865484 Methods for forming templated materials  
Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on...
8852967 Dissolution rate monitor  
A multiple channel site-isolated reactor system and method are described. The system contains a reactor block with a plurality of reactors. Input lines are coupled to each reactor to provide a...
8846448 Warpage control in a package-on-package structure  
The present disclosure relates to a tool arrangement and method to reduce warpage within a package-on-package semiconductor structure, while minimizing void formation within an...