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7625786 Semiconductor device and method of manufacturing the same  
Problems in prior art regarding an n-channel TFT in the source/drain gettering method are solved. In the n-channel TFT, its source/drain regions contain only an n-type impurity. Therefore, compared...
7615435 Semiconductor device and method of manufacture  
A semiconductor device and method of manufacture and, more particularly, a semiconductor device having strain films and a method of manufacture. The device includes an embedded SiGeC layer in...
7611937 High performance transistors with hybrid crystal orientations  
A method of forming a semiconductor structure having a hybrid crystal orientation and forming MOSFETs having improved performance on the semiconductor structure is provided. The method includes...
7611928 Method for producing a substrate  
Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer,...
7608494 Thin film transistor array panel and a method for manufacturing the same  
A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed...
7605027 Method of fabricating a bipolar transistor  
A method of fabricating a bipolar transistor in a first trench ( 11 ) is disclosed wherein only one photolithographic mask is applied which forms a first trench ( 11 ) and a second trench ( 12 ). A...
7598545 Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices  
The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region...
7598540 High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the same  
The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present...
7588973 Semiconductor device and method of manufacturing the same  
In a semiconductor device having a semiconductor element having a plurality of SOI-Si layers, the height of element isolation regions from the surface of the semiconductor substrate are...
7586160 Method of manufacturing a semiconductor integrated circuit and semiconductor integrated circuit  
A semiconductor integrated circuit is provided in which a CMOS transistor is formed on a first conductivity type semiconductor film provided on a first conductivity type supporting substrate...
7585711 Semiconductor-on-insulator (SOI) strained active area transistor  
A selectively strained MOS device such as selectively strained PMOS device making up an NMOS and PMOS device pair without affecting a strain in the NMOS device the method including providing a...
7582516 CMOS devices with hybrid channel orientations, and methods for fabricating the same using faceted epitaxy  
The present invention relates to a semiconductor substrate comprising at least first and second device regions. The first device region has a substantially planar surface oriented along one of a...
7579225 Method of forming semiconductor device having stacked transistors  
There is provided a method of forming a semiconductor device having stacked transistors. When forming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom...
7579223 Semiconductor apparatus and process for fabricating the same  
A semiconductor apparatus in which a conducting path formed from organic semiconductor molecules as a material has a novel structure and exhibits high mobility, and a manufacturing method for...
7575975 Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer  
Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality...
7566600 SOI device with reduced drain induced barrier lowering  
A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high...
7562327 Mask layout design improvement in gate width direction  
In a cell comprising an N well and a P well, a distance SP 04 from a center line of a contact N-type region to an N well end of the N well is set to be a distance which causes a transistor not to...
7560319 Method for fabricating a semiconductor device  
A method of fabricating a semiconductor device includes forming an insulation layer structure on a single-crystalline silicon substrate, forming a first insulation layer structure pattern...
7544549 Method for manufacturing semiconductor device and MOS field effect transistor  
Upon manufacture of a semiconductor device provided with a source region and a drain region formed by activating, through anneal, an n-type first dopant ion-implanted in a p-type device forming...
7544548 Trench liner for DSO integration  
A semiconductor process and apparatus provide a shallow trench isolation region ( 96 ) with a trench liner ( 95, 104 ) for use in a hybrid substrate device ( 21 ) by lining a first trench with a...
7544546 Formation of carbon and semiconductor nanomaterials using molecular assemblies  
The invention is directed to a method of forming carbon nanomaterials or semiconductor nanomaterials. The method comprises providing a substrate and attaching a molecular precursor to the...
7537982 Method and structure for isolating substrate noise  
An integrated circuit structure for isolating substrate noise and a method of forming the same are provided. In the preferred embodiment of the present invention, a semi-insulating region is formed...
7534674 Method of making a semiconductor device with a stressor  
First and second transistors are formed adjacent to each other. Both transistors have gate sidewall spacers removed. A stressor layer is formed overlying the first and second transistors. Stress in...
7531394 Manufacturing method for a TFT LCD array substrate  
The present invention discloses a method for manufacturing a TFT LCD array substrate by utilizing the gray tone mask technology and the photoresist lifting-off technology with only two masks in two...
7528410 Semiconductor device and method for manufacturing the same  
A semiconductor device that can be manufactured with a reduced cost by decreasing the number of masks is disclosed, and a method for manufacturing the semiconductor device is disclosed. The method...
7525159 Turn-on-efficient bipolar structures for on-chip ESD protection  
A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well...
7524710 Radiation-hardened silicon-on-insulator CMOS device, and method of making the same  
A silicon-on-insulator metal oxide semiconductor device comprising ultrathin silicon-on-sapphire substrate; at least one P-channel MOS transistor formed in the ultrathin silicon layer; and N-type...
7510917 Active matrix display device and method of manufacturing the same  
In an active matrix display device integrated with peripheral drive circuits, an image sensor is provided on the same substrate as a pixel matrix and peripheral drive circuits. The image sensor is...
7504289 Process for forming an electronic device including transistor structures with sidewall spacers  
An electronic device can include a first transistor structure including a first gate electrode surrounded by a first sidewall spacer having a first stress and a second transistor structure...
7491588 Method and structure for buried circuits and devices  
A method is provided in which for fabricating a complementary metal oxide semiconductor (CMOS) circuit on a semiconductor-on-insulator (SOI) substrate. A plurality of field effect transistors...
7485521 Self-aligned dual stressed layers for NFET and PFET  
Methods are disclosed for forming self-aligned dual stressed layers for enhancing the performance of NFETs and PFETs. In one embodiment, a sacrificial layer is used to remove a previously deposited...
7485519 After gate fabrication of field effect transistor having tensile and compressive regions  
A field effect transistor (“FET”) is formed to include a stress in a channel region of an active semiconductor region of an SOI substrate. A gate is formed to overlie the active semiconductor...
7485508 Two-sided semiconductor-on-insulator structures and methods of manufacturing the same  
Both sides of a semiconductor-on-insulator substrate are utilized to form MOSFET structures. After forming first type devices on a first semiconductor layer, a handle wafer is bonded to the top of...
7479418 Methods of applying substrate bias to SOI CMOS circuits  
The present invention relates to methods for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a...
7476578 Process for finFET spacer formation  
A process for finFET spacer formation generally includes depositing, in order, a conformal liner material, a conformal spacer material, and a conformal capping material onto the finFET structure;...
7473972 Thin film transistor substrate and method for manufacturing the same  
A thin film transistor substrate includes a thin film transistor of a first conductivity type, a semiconductor layer having a channel region of the first conductivity type placed between the...
7470573 Method of making CMOS devices on strained silicon on glass  
A method of making CMOS devices on strained silicon on glass includes preparing a glass substrate, including forming a strained silicon layer on the glass substrate; forming a silicon oxide layer...
7432149 CMOS on SOI substrates with hybrid crystal orientations  
Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the...
7432144 Method for forming a transistor for reducing a channel length  
A method of forming a transistor including: forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate; forming a low energy ion implantation region aligned with...
7425477 Manufacturing method of thin film transistor including implanting ions through polysilicon island and into underlying buffer layer  
A manufacturing method of a thin film transistor is provided. A buffer layer is formed on a substrate, and then a first and a second poly-silicon island are formed thereon. A gate-insulating layer...
7422971 Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby  
The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack...
7419859 Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions  
Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures,...
7416927 Method for producing an SOI field effect transistor  
Method for producing a first SOI field effect transistor with predetermined transistor properties by forming a laterally delimited layer sequence with a gate-insulating layer and a gate region on...
7413939 Method of growing a germanium epitaxial film on insulator for use in fabrication of CMOS integrated circuit  
A method of fabricating a silicon-germanium CMOS includes preparing a silicon substrate wafer; depositing an insulating layer on the silicon substrate wafer; patterning and etching the insulating...
7410842 Method for fabricating thin film transistor of liquid crystal display device  
A method for fabricating a thin film transistor for an LCD device is presented that uses six mask processes. Portions of a semiconductor layer formed on a substrate are doped with first and second...
7405112 Low contact resistance CMOS circuits and methods for their fabrication  
A low contact resistance CMOS integrated circuit and method for its fabrication are provided. The CMOS integrated circuit comprises a first transition metal electrically coupled to the N-type...
7402466 Strained silicon CMOS on hybrid crystal orientations  
Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a...
7399662 Method of manufacturing a thin film transistor device  
A method of making a thin film transistor device, including forming and patterning a semiconductor film to form first and second semiconductor films in, respectively, low-voltage driven and...
7396714 Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions  
A process is provided for making a PFET and an NFET. Areas in a first semiconductor region adjacent to a gate stack are recessed. A lattice-mismatched semiconductor layer is grown in the recesses...
7374981 Thin film transistor, electronic device having the same, and method for manufacturing the same  
An object of the present invention is to provide a method for manufacturing a thin film transistor which enables heat treatment aimed at improving characteristics of a gate insulating film such as...
Matches 1 - 50 out of 342 1 2 3 4 5 6 7 >