|
Match
|
Document |
Document Title |
|
|
7615422 |
Evaluation method of semiconductor device, manufacturing method of the semiconductor device, design management system of device comprising the semiconductor device, dose amount control program for the semiconductor device, computer-readable recording medium recording the program, and dose amount control apparatus
There is provided a new method of obtaining the dopant activation rate of a device accurately and simply in a different way from a method of obtaining a carrier density with use of a Hall...
|
|
|
7608469 |
Method of fabricating a chip
A method of fabricating a chip may include the step of providing a first electrical part. The method may also include the step of forming a shell with the first electrical part embedded in a first...
|
|
|
7601559 |
Apparatus and method for identifying proper orientation and electrical conductivity between a semiconductor device and a socket or contactor
A semiconductor device with a semiconductor die thereon and a contactor board are electrically coupled when the electrically conductive elements on the semiconductor device and the contactor board...
|
|
|
7598100 |
Manufacturing method of semiconductor integrated circuit device
As the thickness of the card holder for preventing warping of a multilayered wiring substrate 1 is increased, there occurs a problem that a thin film sheet 2 is buried in a card holder and...
|
|
|
7582542 |
Die attaching method
A die attaching method for attaching semiconductor dies on wafers, each wafer having a first center point and a first radius may include expanding a wafer carrier tape so that the wafer has a...
|
|
|
7582494 |
Device structures for reducing device mismatch due to shallow trench isolation induced oxides stresses
A circuit and method are disclosed for reducing device mismatch due to trench isolation related stress. One or more extended active regions are formed on the substrate, wherein the active regions...
|
|
|
7566575 |
Mounting circuit and method for producing semiconductor-chip-mounting circuit
A method according to the present invention for producing a semiconductor-chip-mounting circuit 1 includes mainly three steps. In a first step, contacts 2 each in the form of a conical helix...
|
|
|
7557597 |
Stacked chip security
The present invention is directed to an integrated circuit module device. The device includes a first semiconductor chip having a first circuit layer and at least one first interconnection element...
|
|
|
7556973 |
Manufacturing method for semiconductor device
A Manufacturing method for a semiconductor device is provided and includes examining a semiconductor element on a semiconductor wafer, by an on-wafer test, storing on-semiconductor-wafer coordinate...
|
|
|
7553681 |
Carbon nanotube-based stress sensor
An embodiment of the present invention is a technique to form stress sensors on a package in situ. A first array of carbon nanotubes (CNTs) aligned in a first orientation is deposited at a first...
|
|
|
7553680 |
Methods to provide and expose a diagnostic connector on overmolded electronic packages
An overmolded electronic assembly is provided having a circuit board with electronic devices and a diagnostic connection. The diagnostic connection includes electrical conductors having a distal...
|
|
|
7553679 |
Method of determining plasma ion density, wafer voltage, etch rate and wafer current from applied bias voltage and current
Plasma parameters such as plasma ion density, wafer voltage, etch rate and wafer current in the chamber are determined from external measurements on the applied RF bias electrical parameters such...
|
|
|
7549560 |
Wafer dividing method
A method of dividing a wafer along a plurality of first dividing lines and a plurality of second dividing lines intersecting with the first dividing lines on the surface of the wafer. The method...
|
|
|
7524684 |
Semiconductor device with electrode pad having probe mark
A semiconductor device is formed by bonding bonding balls to a plurality of electrode pads formed on a semiconductor chip. After a wafer test is conducted by pressing a probe against the electrode...
|
|
|
7514276 |
Aligning stacked chips using resistance assistance
The present invention relates to a method of aligning stacked chips wherein the apparatus and method utilize bumps in the form of exposed metal lines on a first chip. The present invention further...
|
|
|
7514274 |
Enhanced uniqueness for pattern recognition
The present invention describes a test structure with a first set of features which is a subset of product features; and a second set of features adjacent to the first set of features, the second...
|
|
|
7507633 |
Method and structure for improved alignment in MRAM integration
A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the structure, the second set of alignment...
|
|
|
7498678 |
Electronic assemblies and systems with filled no-flow underfill
High yield, high reliability, flip-chip integrated circuit (IC) packages are achieved utilizing a combination of heat and pressure to bond flip-chip die and to cure no-flow underfill material. The...
|
|
|
7498192 |
Methods of providing a family of related integrated circuits of different sizes
Methods of manufacturing a family of packaged integrated circuits (ICs) having at least two different logic capacities. A first IC die includes two different portions, of which at least one portion...
|
|
|
7498181 |
Method of preparing an integrated circuit die for imaging
Integrated circuit dies are prepared for imaging by completely etching away all metal from the metal lines without removing barrier layers that underlie the metal lines. The metal vias may also be...
|
|
|
7494828 |
Substrate holder and device manufacturing method
A second substrate, e.g. a III/V compound semiconductor, is placed on a first substrate, e.g. a wafer, in the vicinity of placement marks on the first substrate. The second substrate is exposed to...
|
|
|
7491556 |
Efficient method of forming and assembling a microelectronic chip including solder bumps
The present invention provides a new technology approach for forming a contact layer in a microelectronic chip, which includes a plurality of solder bumps that are directly to be connected with a...
|
|
|
7485489 |
Electronics circuit manufacture
A circuit with embedding components ( 13 ) is produced by placing the components ( 13 ) on a substrate ( 14 ) and applying sheets ( 15 ) of prepreg. The prepreg sheets ( 15 ) have apertures to...
|
|
|
7482180 |
Method for determining the impact of layer thicknesses on laminate warpage
A method for analyzing the warpage of organic laminates used in flip chip packages includes collecting warpage data and layer thickness data for several laminates. A principal components analysis...
|
|
|
7478022 |
Component emulation device and method of design
A robust component emulator is provided for use in enclosure testing. Characteristics of the emulator are selected in accordance with the enclosure's view of the component during enclosure testing....
|
|
|
7476555 |
Method of chip manufacturing
A method of chip manufacturing, comprises of a design stage; a simulation stage; a foundry stage; a testing/packaging stage; a cutting stage; and a final coating stage. The present invention...
|
|
|
7476553 |
Transfer base substrate and method of semiconductor device
A transfer base substrate comprises: a substrate; a plurality of transfer thin film circuits formed on the substrate via removing layer; a test circuit formed on the substrate for checking circuit...
|
|
|
7468525 |
Test structures for development of metal-insulator-metal (MIM) devices
In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode...
|
|
|
7468309 |
Semiconductor wafer treatment method
A semiconductor wafer treatment method for dividing an adhesive tape, which has been stuck to the entire back of a semiconductor wafer, along divided streets of the semiconductor wafer. Before...
|
|
|
7452733 |
Method of increasing reliability of packaged semiconductor integrated circuit dice
Semiconductor dice are electrically tested prior to final assembly. Dice failing the test are identified and not packaged. However, “good dice” (i.e., those dice that passed testing) in...
|
|
|
7452732 |
Comparing identifying indicia formed using laser marking techniques to an identifying indicia model
A laser marking apparatus and method for marking the surface of a semiconductor chip are described herein. A laser beam is directed to a location on the surface of the chip where a laser-reactive...
|
|
|
7449362 |
One-component hot-setting epoxy resin composition and semiconductor mounting underfill material
The present invention provides an one-pack thermosetting type epoxy resin composition which is useful as an underfilling material used when a flip chip or a semiconductor package comprised of a...
|
|
|
7445959 |
Sensor module and method of manufacturing same
The embodiments herein relate to sensor modules having sensor chips with a sensing region on a face thereof, and methods for their manufacture.
|
|
|
7444012 |
Method and apparatus for performing failure analysis with fluorescence inks
A method for performing failure analysis on a semiconductor device under inspection includes preparing of a device sample using an encapsulation material containing a dye, the prepared device...
|
|
|
7442576 |
Placement of absorbing material in a semiconductor device
A semiconductor device is provided that includes a hermetically sealed housing having a top member and a bottom member. A semiconductor die is enclosed within the housing and absorbing material is...
|
|
|
7442559 |
Method for producing an optical or electronic module provided with a plastic package
A method for producing an optical or electronic module provided with a plastic package including: providing at least one optical or electronic component, the component having an operative region,...
|
|
|
7439168 |
Apparatus and method of forming silicide in a localized manner
Localized trenches or access holes are milled in a semiconductor substrate to define access points to structures of an integrated circuit intended for circuit editing. A conductor is deposited,...
|
|
|
7439090 |
Method for manufacturing a lower substrate of a liquid crystal display device
A method for manufacturing a lower substrate of a liquid crystal display device is disclosed and more particularly, a method for manufacturing a color filter layer on a lower substrate is...
|
|
|
7433229 |
Flash memory device with shunt
A shunt activation signal is transmitted by an external control terminal through an external transmission interface to switch a flash memory controller in a shunt mode. The shunt activation signal...
|
|
|
7429497 |
Hybrid package with non-insertable and insertable conductive features, complementary receptacle, and methods of fabrication therefor
A hybrid electronic circuit package ( 102, FIG. 1 ) includes non-insertable conductive features ( 110 ) and insertable conductive features ( 112 ) at a surface of the package. A hybrid receptacle...
|
|
|
7427520 |
Method and apparatus for measuring thickness of thin film formed on substrate
A memory ( 43 ) of a control unit ( 4 ) stores correction data ( 81 ) indicating a relationship between a decrement in a measurement value of a film thickness by removal of organic contamination...
|
|
|
7427517 |
Stacking apparatus and method for stacking integrated circuit elements
A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move...
|
|
|
7423286 |
Laser transfer article and method of making
The present invention is directed to methods for transferring pre-formed electronic devices, such as transistors, resistors, capacitors, diodes, semiconductors, inductors, conductors, and...
|
|
|
7422914 |
Fabrication method of semiconductor integrated circuit device
A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are...
|
|
|
7416910 |
Pyramid socket suspension
An apparatus and method for flexibly suspending a sensing mechanism between a pair of cover plates, including a sensing mechanism formed in a crystalline silicon substrate; a pair of cover plates...
|
|
|
7414323 |
Tab tape and method of manufacturing the same
Input test pads of an adjacent pattern area are placed in a vacant area of a layout area of output test pads, optimizing the layout area of test pads for use in inspection of a semiconductor chip....
|
|
|
7407822 |
Method for inspecting insulating film for film carrier tape for mounting electronic components thereon, inspection apparatus for inspecting the insulating film, punching apparatus for punching the insulating film, and method for controlling the punching apparatus
The invention provides an inspection apparatus and an inspection method for detecting defects, a punching apparatus, and a method for controlling a punching apparatus, for the purpose of immediate...
|
|
|
7405103 |
Process for fabricating chip embedded package structure
A process for fabricating a chip embedded package structure is provided. A stiffener is disposed on a tape. A chip is disposed on the tape inside a chip opening of the stiffener such that an active...
|
|
|
7393754 |
Tape carrier type semiconductor device and method of producing the same
A tape carrier type semiconductor device comprising: a long flexible insulating tape; and a plurality of semiconductor devices sequentially arranged on one surface of the tape, wherein each...
|
|
|
7391119 |
Temperature sustaining flip chip assembly process
A temperature sustaining flip chip process in which ILD cracking and delamination are lessened. A sequence of substrate prebake, underfill dispense, chip placement, solder reflow and underfill cure...
|