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6605824 |
Semiconductor drive
The invention relates to a semiconductor device comprising a bond pad structure, which bond pad structure enables analyses to be carried out at a level of a metal layer of the semiconductor device...
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6605479 |
Method of using damaged areas of a wafer for process qualifications and experiments, and system for accomplishing same
In one illustrative embodiment, the method comprises providing a wafer, forming a plurality of die above the wafer, identifying a plurality of good die and at least one non-useful die from the...
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6602762 |
System and method of laser sintering dies and dies sintered by laser sintering
A laser sintering system is provided for sintering a die having a serrate edge. The laser sintering system comprises a laser generator for generating a laser beam and a movable carriage for...
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6599764 |
Isolation testing scheme for multi-die packages
A test platform is configured to test a mult-die package having at a first die and a second die. The test platform includes a first lead that is connected to the VCC input on the first die. The...
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6593590 |
Test structure apparatus for measuring standby current in flash memory devices
A flash memory microelectronic chip ( 1000 ) is formed with at least one integral test structure ( 100 ) for electrical measurement of transistor leakage current from the low voltage peripheral...
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6589801 |
Wafer-scale production of chip-scale semiconductor packages using wafer mapping techniques
A method is disclosed for manufacturing chip-scale semiconductor packages at a wafer-scale level using wafer mapping techniques. In the method, a semiconductor wafer and/or a circuit substrate,...
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6589860 |
System and method for calibrating electron beam defect inspection tool
A system and method for calibrating/characterizing an electron beam (e-beam) defect inspection tool for detecting voltage contrast defects includes deliberately forming defects in a test portion of...
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6590409 |
Systems and methods for package defect detection
A charged particle imaging system may be used to perform package-level failure analysis by providing a Capacitive Coupling Voltage Contrast image of a portion of the semiconductor package....
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6589802 |
Packaging structure and method of packaging electronic parts
The present invention a structure in which a semiconductor integrated circuit chip can be easily removed and the reliability of flip-chip bonding is assured, a method of packaging electronic parts,...
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6579734 |
Wire bonding method
A semiconductor device is provided which is obtained by wire bonding without any drop in wire bonding characteristics. A bonding pad is prepared on which a wire bonding region and a test region...
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6579733 |
Using scatterometry to measure resist thickness and control implant
The present invention provides systems and methods wherein scatterometry is used to control an implant processes, such as an angled implant process. According to the invention, data relating to...
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6573112 |
Semiconductor device manufacturing method
Semiconductor device chips manufacturing and inspecting method is disclosed in which a semiconductor wafer is cut into individual LSI chips. The LSI chips are rearranged and integrated into a...
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6569693 |
Method for fabricating epitaxial substrate
Provided is a method for fabricating a compound semiconductor multilayer epitaxial substrate comprising a plurality of epitaxial layers, comprising the steps of determining at least one of the...
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6565720 |
Substrate removal as a function of sputtered ions
Substrate removal from a semiconductor chip having silicon-on-oxide (SOI) structure is enhanced via a method and system that provide a control for the removal process. According to an example...
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6565667 |
Process for cleaning ceramic articles
A method for cleaning an inorganic surface of a virgin semiconductor processing component by directing a flow of frozen CO 2 pellets upon the surface. After cleaning, the component is packaged for...
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6562638 |
Integrated scheme for predicting yield of semiconductor (MOS) devices from designed layout
A method for determining device yield of a semiconductor device design, includes determining statistics of at least one MOSFET parameter from a gate pattern, and calculating device yield from the...
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6562640 |
Method of manufacturing micro-display
A method of manufacturing micro-display includes the steps of testing individual chips on a base wafer forming the micro-display, and the tested “void” chips being marked, inputting the testing...
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6558966 |
Apparatus and methods of packaging and testing die
Apparatus and methods of packaging and testing die. In one embodiment, a stacked die package includes a packaging substrate having a first surface with a recess disposed therein and a plurality of...
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6555400 |
Method for substrate mapping
A method and apparatus relating to fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a...
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6555399 |
Double-packaged multichip semiconductor module
A method for forming a semiconductor component comprises packaging a plurality of semiconductor die into one component. Present designs comprise multiple unpackaged die which have been probed, but...
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6555413 |
Method for interconnecting semiconductor elements to form a thermoelectric cooler and a thermoelectric cooler formed therefrom
A method for electrically coupling thermoelectric cooling (TEC) elements together is described. The TEC elements are encased within an encapsulating material, such as epoxy, and a resist layer is...
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6551906 |
Method of fabricating semiconductor device
A method of fabricating a semiconductor device is provided in which a protective tape for back grinding is adhered to a front surface of a wafer and back grinding processing is carried out....
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6551845 |
Method of temporarily securing a die to a burn-in carrier
A method of using adhesive tape to temporarily retain a die being temporarily held in a fixture during testing and burn-in. The method of the present invention uses a die cut piece of adhesively...
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6551861 |
Method of making a semiconductor chip assembly by joining the chip to a support circuit with an adhesive
A method of manufacturing a semiconductor chip assembly includes providing a semiconductor chip that includes a conductive pad, and providing a support circuit that includes an insulative base, a...
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6548314 |
Method for enabling access to micro-sections of integrated circuits on a wafer
The present invention provides a method of enabling measurement access to small integrated circuit features that comprises selecting a feature of an integrated circuit on a wafer and providing...
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6541289 |
Semiconductor-package measuring method, measuring socket, and semiconductor package
Electrical connection of a measuring socket to an IC package, to measure electrical characteristics of the IC package, is realized by bringing a measuring pin of a measuring arm of the measuring...
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6537833 |
Method and apparatus for characterizing an interconnect structure profile using scatterometry measurements
A method for characterizing an interconnect structure profile includes providing a wafer having a grating structure including a plurality of interconnect structures; illuminating at least a portion...
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6534786 |
Semiconductor device having a test element, and method of manufacturing the same
In a TEG area, a conductive layer for a storage node is electrically connected through an impurity region positioned beneath the layer to an aluminum interconnection layer. In this manner, a test...
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6528332 |
Method and system for reducing polymer build up during plasma etch of an intermetal dielectric
A method and system for deprocessing a semiconductor device is disclosed. The semiconductor device has a plurality of structures and an intermetal dielectric layer. The method and system include...
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6528349 |
Monolithically-fabricated compliant wafer-level package with wafer level reliability and functionality testability
Compliant wafer level packages 10 and methods for monolithically fabricating the same. A monolithically fabricated compliant wafer level package 10 having a compliant layer 14 and a compliant...
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6528329 |
Method for stabilizing temperature of an optoelectronic module
An optoelectronic module and a method for stabilizing its temperature are disclosed wherein the measurement of the reference temperature for the temperature sensor takes place on the substrate...
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6525528 |
ROM automatic burning device
An automatic ROM burning device, comprising a support plate that is erected almost vertically. On the surface of the support plate is at least one feeder chute, inside which is inserted an IC rod,...
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6521910 |
Structure of a test key for monitoring salicide residue
A structure of a test key for monitoring self-aligned silicide (salicide) residues has of a silicon substrate, multiple parallel diffusion regions formed on the silicon substrate, multiple...
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6521479 |
Repackaging semiconductor IC devices for failure analysis
The present invention provides a system and method for preparing semiconductor integrated circuits (“ICs”), particularly ball grid arrays (“BGAs”), quad flat packs (“QFPs”) and dual in...
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6514777 |
Built-in inspection template for a printed circuit
An improved bonding strip for a printed circuit to facilitate quality inspection. The bonding strip has functional regions and non-functional regions. A functional region is indicated by an area of...
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6514779 |
Large area silicon carbide devices and manufacturing methods therefor
A silicon carbide device is fabricated by forming a plurality of a same type of silicon carbide devices on at least a portion of a silicon carbide wafer in a predefined pattern. The silicon carbide...
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6506615 |
Method for measuring the depth of well
The present invention is directed to an effective and relatively inexpensive way to measuring the depth of a well in a semiconductor device. In accordance with an aspect of the present invention, a...
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6500682 |
Method for configuring a redundant bond pad for probing a semiconductor
An integrated device includes a redundant bond pad for accessing internal circuitry in the event that the main bond pad for that circuitry is difficult to access with testing equipment. Signals...
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6500685 |
Method for evaluating molding material with dams formed on a semiconductor substrate to define slits for capturing fillers contained in the molding material
A test chip for a molding material including fillers, including, a semiconductor substrate and a test circuit formed on the substrate. The test circuit includes at least one transistor, and two...
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6500684 |
Method and apparatus of manufacturing semiconductor device
A method of manufacturing a semiconductor device comprising the steps of: preparing a flexible substrate which includes a base substrate having a light transmission property and an interconnecting...
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6498361 |
Design information memory for configurable integrated circuits
On a wafer that includes multiple distinct designs in each die region, a memory is included in each die region. The memory stores information specific to the design implemented in the same die...
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6495856 |
Semiconductor device having a test pattern same as conductive pattern to be tested and method for testing semiconductor device for short-circuit
A semiconductor random access memory device has stacked capacitor electrodes and test conductive pieces laid on the same pattern as the stacked capacitor electrodes, and the test conductive pieces...
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6492187 |
Method for automatically positioning electronic die within component packages
A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the...
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6485991 |
System and method for output track unit detection and safe storage tube removal
Systems and methods are disclosed for testing semiconductor devices, using a tester providing tested semiconductor devices to a device output track, which feeds the semiconductor devices into a...
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6485992 |
Process for making wafers for ion implantation monitoring
A process is disclosed for making a silicon wafer with low and uniform surface stress by growing at least approximately 8 angstroms of silicon oxide thereon to produce a wafer for use as a control...
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6479310 |
Method for testing a semiconductor integrated circuit device
An apparatus and methods for testing a semiconductor integrated circuit are disclosed. One embodiment includes a method for making a pass/fail determination in a semiconductor integrated circuit...
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6475822 |
Method of making microelectronic contact structures
Spring contact elements are fabricated by depositing at least one layer of metallic material into openings defined on a sacrificial substrate. The openings may be within the surface of the...
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6476414 |
Semiconductor device
In order to precisely estimate a gate length of a MOS transistor in a semiconductor device, the semiconductor device comprises a pair of MOS transistors having different gate lengths. A threshold...
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6472235 |
Apparatus and method for preparing backside-ground wafers for testing
A method and an apparatus for preparing a backside-ground wafer for testing are described. The method includes the steps of first providing a calibration wafer that has a pattern formed on a top...
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6472234 |
Failure analysis method for chip of ball grid array type semiconductor device
In a failure analysis method for a ball grid array type semiconductor device including a semiconductor chip having pads, first solder balls, an interposer substrate and second solder balls, the...
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