|
Match
|
Document |
Document Title |
|
|
6884146 |
Systems and methods for characterizing a polishing process
Systems and methods for characterizing a polishing process are provided. One method includes scanning a specimen with two or more measurement devices during polishing. In one embodiment, the two or...
|
|
|
6884638 |
METHOD OF FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE BY DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING AN OVERDRIVE CURRENT MEASUREMENT TECHNIQUE AND A DEVICE THEREBY FABRICATED
A method for fabricating a flash memory device by determining the active region width ( 10 ) of a semiconductor device ( 27 ) using a measuring technique for the source drain overdrive current...
|
|
|
6884642 |
Wafer-level testing apparatus and method
A semiconductor component configured for wafer-level testing includes a semiconductor die having at least one die contact electrically exposed for coupling with a redistribution circuit that...
|
|
|
6881593 |
Semiconductor die adapter and method of using
A semiconductor die adapter assembly includes a semiconductor die cut from a wafer, the die having an active surface including bond pads. A die adapter, also having bond pads, is bonded to the...
|
|
|
6872582 |
Selective trim and wafer testing of integrated circuits
A method of selective trim and wafer testing of precision integrated circuits is provided by determining if a sample die is within specification. If so the sample parameters are measured and if the...
|
|
|
6869811 |
Methods for transfer molding encapsulation of a semiconductor die with attached heat sink
A semiconductor device includes a heat sink adjacent to a die. A dam is positioned at the peripheral edges of the heat sink. During a transfer molding process, the dam serves two purposes. First,...
|
|
|
6869808 |
Method for evaluating property of integrated circuitry
There are provided a method for evaluating, in a reduced number of steps, a property of an integrated circuit reflecting operating conditions for an actual LSI and the design of the LSI. The...
|
|
|
6869832 |
Method for planarizing bumped die
According to one embodiment of the invention, a method for planarizing bumped die includes providing a die having a plurality of stud bumps, encapsulating the stud bumps with an epoxy-based...
|
|
|
6861750 |
Ball grid array package with multiple interposers
Electrically, thermally and mechanically enhanced ball grid array (BGA) packages are described. An IC die is mounted to a first surface of a first stiffener. A peripheral edge portion of a second...
|
|
|
6861269 |
Electric-circuit fabricating method and system, and electric-circuit fabricating program
A method of fabricating an electric circuit, including first and second working processes of performing respective first and second working operations on a circuit substrate, where3in the first...
|
|
|
6858453 |
Integrated circuit package alignment feature
An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially...
|
|
|
6858447 |
Method for testing semiconductor chips
A method for testing semiconductor chips, in particular semiconductor memory chips, is described. In which, in a chip to be tested, at least one test mode is set, the test mode is executed in the...
|
|
|
6852552 |
Process for selective deposition of material on biosensor or chip electrodes made on the same substrate
A process for selective deposition of material on electrodes of chips made from a single substrate. The process includes forming a plurality of chips on the same substrate. Each chip includes a...
|
|
|
6852553 |
Semiconductor device fabrication method and semiconductor device fabrication apparatus
A method of manufacturing a semiconductor device able to reduce the number of manufacturing steps and attain the rationalization of a manufacturing line is disclosed. The semiconductor device is a...
|
|
|
6842662 |
Method and apparatus for fully aligned flip-chip assembly having a variable pitch packaging substrate
A method and an apparatus for preventing misalignment of semiconductor packaging assembly materials. In particular, a method of fabricating a fully aligned flip-chip assembly having a variable...
|
|
|
6838751 |
Multi-row leadframe
A leadframe ( 20 ) for a semiconductor device includes a paddle ring ( 22 ) having an inner perimeter ( 24 ), an outer perimeter ( 26 ), and a cavity ( 28 ) located within the inner perimeter ( 24...
|
|
|
6835579 |
Method of monitoring internal voltage and controlling a parameter of an integrated circuit
An integrated circuit (I/C) assembly includes a dedicated voltage sensor line for determining with a high degree of accuracy the operating voltage at a predetermined sensor point on the IC die. The...
|
|
|
6835580 |
Direct chip attach structure and method
A method for forming a direct chip attach (DCA) device ( 1 ) includes attaching a chip ( 3 ) to a lead frame ( 2 ). Conductive studs ( 22 ) are attached to bonding pads ( 13 ) on the chip ( 3 ) and...
|
|
|
6833277 |
Method and system for field assisted statistical assembly of wafers
A wafer having heterostructure therein is formed using a substrate with recesses formed within a dielectric layer. A magnetized magnetic layer or a polarized electret material is formed at the...
|
|
|
6830938 |
Method for improving retention reliability of ferroelectric RAM
The present invention can improve and/or modify data retention lifetimes for ferroelectric devices by baking them prior to or during packaging. A ferroelectric device is programmed to a particular...
|
|
|
6822260 |
Linewidth measurement structure with embedded scatterometry structure
A method of manufacturing a semiconductor device includes depositing a layer over a substrate and etching the layer to form a grating structure, a cross bridge test structure and a line width...
|
|
|
6821796 |
Method and system for temperature cycling at an interface between an IC die and an underfill material
For temperature cycling at a material of an IC (integrated circuit) package, a laser beam is directed to the material such that the material absorbs the laser beam to become heated. A laser...
|
|
|
6818479 |
Highly moisture-sensitive electronic device element and method for fabrication
A highly moisture-sensitive element and method of making such element includes an encapsulation enclosure encapsulating all of the highly moisture-sensitive electronic devices on a substrate and a...
|
|
|
6818460 |
Method for applying adhesives to a lead frame
A method for applying a viscous material to a lead frame element. A method of the invention includes positioning the lead frame facing downward and bringing the lead fingers into contact with a...
|
|
|
6818461 |
Method of producing mounting structure and mounting structure produced by the same
A mounting structure is formed by flip-chip mounting a semiconductor device onto a substrate. An electrical connecting portion of the semiconductor device is connected to an electrical connecting...
|
|
|
6815712 |
Method for selecting components for a matched set from a wafer-interposer assembly
A matched set of integrated circuit chips ( 24 ) and a method for assembling such integrated circuit chips ( 24 ) into a matched set are disclosed. A semiconductor wafer ( 18 ) having a plurality...
|
|
|
6815234 |
Reducing stress in integrated circuits
A semiconductor chip in which stress on the effective stress on the substrate is reduced in order to reduce bowing. To reduce the effective stress, a stress compensation layer is provided on the...
|
|
|
6815230 |
Control signal transmitting method with package power pin and related integrated circuit package structure
A method and a device are disclosed for transmitting a control signal to an option pad of an integrated circuit chip at its package level. The method includes the steps of: electrically isolating...
|
|
|
6812045 |
Methods and systems for determining a characteristic of a specimen prior to, during, or subsequent to ion implantation
Methods and systems for monitoring semiconductor fabrication processes are provided. A system may include a stage configured to support a specimen and coupled to a measurement device. The...
|
|
|
6809044 |
Method for making a thin film using pressurization
The invention relates to a process for making a thin film starting from a substrate ( 1 ) of a solid material with a plane face ( 2 ) comprising: the implantation of gaseous compounds in the...
|
|
|
6806725 |
Method and apparatus for processing an array of packaged semiconductor devices
The invention provides a method and apparatus for processing an array of electronic components. It involves providing mounting means to mount unsingulated components onto the mounting means,...
|
|
|
6806494 |
Method and apparatus for wafer-level burn-in and testing of integrated circuits
In one embodiment, a testing regimen is implemented to reduce test time. Specifically, a structure and method to power up and stabilize all die on the wafer prior to testing each die is...
|
|
|
6800494 |
Method and apparatus for controlling copper barrier/seed deposition processes
The present invention is generally directed to various methods of controlling copper barrier/seed deposition processes, and a system for accomplishing same. In one illustrative embodiment, the...
|
|
|
6801096 |
Ring oscillator with embedded scatterometry grate array
A MOS ring oscillator includes a number of serially connected inverter stages with each stage comprising a MOS transistor pair. At least one of the transistors also comprises a scatterometry grate...
|
|
|
6800508 |
Semiconductor device, its manufacturing method and electrodeposition frame
A semiconductor device includes: a semiconductor element 2 bonded on a first metallic layer; a wire 4 for electrically connecting an electrode pad of the semiconductor element to a second...
|
|
|
6794203 |
Method of calculating the real added defect counts
The present invention provides a method of producing an added defect count for monitoring the property of chambers or wafers. First, a proper pre-process sensitivity is determined with map to map...
|
|
|
6794205 |
Chip scale marker and method of calibrating marking position
A chip scale marker including a laser system, a wafer holder supporting a wafer to be processed, and a camera moving above the wafer holder by being connected to an X-Y stage and monitoring the...
|
|
|
6790687 |
Substrate processing apparatus and semiconductor device producing method
A substrate processing apparatus includes a processing chamber which processes a substrate; a substrate supporting body which supports the substrate in the processing chamber; a heating member...
|
|
|
6790684 |
Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing
A semiconductor device wafer-on-support wafer package comprising a plurality of segmentable chip-scale packages and method of constructing, burning-in, and testing same are disclosed. The...
|
|
|
6790708 |
Encapsulation process using a partial slot cover and a package formed by the process
A system and method for encapsulating an integrated circuit package. More specifically, a system and method for encapsulating a board-on-chip package is described. A strip of material is disposed...
|
|
|
6787375 |
Microelectronic fabrication die electrical test method providing enhanced microelectronic fabrication die electrical test efficiency
Within a method for electrical testing a series of microelectronic fabrication die fabricated within a microelectronic fabrication substrate, there is first electrically tested the series of...
|
|
|
6787803 |
Test patterns for measurement of low-k dielectric cracking thresholds
The present invention provides two or more test structures/substructures ( 100 ) that are used in a test pattern ( 500, 600, 700, 800 ) to determine a cracking threshold for a dielectric material (...
|
|
|
6787374 |
Semiconductor device manufacturing method and semiconductor device sorting system to be used with the same
A sorting section can be supplied with parts from plurality of supply sources. A semiconductor device sorting system is provided with a sorting section for sorting good transistors by means of an...
|
|
|
6784001 |
Automated variation of stepper exposure dose based upon across wafer variations in device characteristics, and system for accomplishing same
A novel method and system for fabricating integrated circuit devices is disclosed herein. In one embodiment, the method comprises determining at least one electrical performance characteristic of a...
|
|
|
6781232 |
Sample preparation apparatus and method
A apparatus and method for forming windows in semiconductor devices to enable visualization of the circuitry therein while electrically intact. The device is affixed to a table that is oscillated...
|
|
|
6781218 |
Method and apparatus for accessing internal nodes of an integrated circuit using IC package substrate
A method and apparatus for accessing internal nodes of an integrated circuit using a package substrate are provided. Embodiments of the present invention include an integrated circuit comprising an...
|
|
|
6777251 |
Metrology for monitoring a rapid thermal annealing process
A method including operating an ion implanted to implanting ions in a semiconductor wafer at a first ion dose level; performing a first thermal wave measurement to obtain the first thermal wave...
|
|
|
6774659 |
Method of testing a semiconductor package device
A method of testing a semiconductor package device includes providing a device that includes an insulative housing, a semiconductor chip, a terminal and a lead, wherein the terminal protrudes...
|
|
|
6773938 |
Probe card, e.g., for testing microelectronic components, and methods for making same
Various aspects of the invention provide methods of manufacturing probe cards and test systems which may test microelectronic components using such probe cards. In one specific example, a probe...
|
|
|
6770847 |
Method and system for Joule heating characterization
According to one exemplary embodiment, a method for establishing a relationship between Joule heating in a conductor and a current density in the conductor is implemented by performing wafer level...
|