Matches 151 - 200 out of 726 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
7105379 Implementation of protection layer for bond pad protection  
A method of protecting a bond pad during die-sawing comprising the following steps. A substrate having a bond pad formed thereover is provided. A bond pad protection layer is formed over the bond...
7105366 Method for in-line testing of flip-chip semiconductor assemblies  
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or...
7101721 Adaptive manufacturing for film bulk acoustic wave resonators  
An adaptive manufacturing process for a Film Bulk Acoustic Resonator (FBAR) tests the FBAR circuit during manufacturing to determine a resonant frequency thereof. Reactive tuning elements may be...
7098051 Structure and method of direct chip attach  
A semiconductor package ( 101 ) has a die ( 1 ), a leadframe ( 4 ), a bond pad ( 6 ), an encapsulation ( 3 ) and a wire bond ball ( 2 ). The wire bond ball is formed on the bond pad by bonding one...
7087442 Process for the formation of a spatial chip arrangement and spatial chip arrangement  
Process for the formation of a spatial chip arrangement having several chips ( 32, 36, 37, 38, 39 ) arranged in several planes and electrically connected to one another, in which the chips are...
7084511 Semiconductor device having resin-sealed area on circuit board thereof  
A semiconductor device having a molded sealing resin for sealing a semiconductor chip on a circuit board thereof reduces resin burrs resulting from the leakage of the sealing resin, and also...
7074627 Lead solder indicator and method  
A solder system includes a lead (Pb) indicator and a solder flux. A method for forming a semiconductor device includes providing a carrier, applying the solder system to the carrier, coupling the...
7071031 Three-dimensional integrated CMOS-MEMS device and process for making the same  
A vertically integrated structure includes a micro-electromechanical system (MEMS) and a chip for delivering signals to the MEMS. The structure includes a metal stud connecting a surface of the...
7067334 Tape carrier package and method of fabricating the same  
A tape carrier package with a widow that is capable of confirming an alignment extent between the tape carrier package and a print wiring board in bonding the tape carrier package mounted with an...
7063987 Backside failure analysis of integrated circuits  
Backside failure analysis of integrated circuits. In one embodiment, a method of preparing a device under test (DUT) for an image based diagnostic testing is disclosed. The method comprises...
7060511 Evaluation method of a field effect transistor  
The present invention provides a method for estimating resistance value of an LDD region that works in an actual FET and forming an optimum LDD region. Therefore, the present invention provides an...
7056819 Methods and apparatus for determining pad height for a wire-bonding operation in an integrated circuit  
Methods and apparatus for performing a wire-bonding operation in an integrated circuit are disclosed. The positions of at least one height-sensing pad and at least one bond pad are determined on a...
7054705 Method of manufacturing semiconductor devices  
A semiconductor device manufacturing system is provided in which chip position information is read without removing resin from a package so that the cause of a failure can be quickly identified and...
7050922 Method for optimizing test order, and machine-readable media storing sequences of instructions to perform same  
In a test order optimization method, a pass probability and resource requirement are identified for each of a plurality of tests. A pass-weighted resource requirement factor is then generated for...
7045387 Method of performing back-end manufacturing of an integrated circuit device  
A method of performing back-end manufacturing of an integrated circuit (IC) device is disclosed. In one method embodiment, the present invention processes a die-strip through a front-of-line...
7041516 Multi chip module assembly  
A method of assembling at least a first integrated circuit and a second integrated circuit into a multi chip module. The first integrated circuit is attached and electrically connected to a first...
7040012 Method of electrically and mechanically connecting electronic devices to one another  
A method is provided for electrically and mechanically connecting a first electronic device to a second electronic device. At least one electric contact of the first device is located against an...
7041515 Balancing planarization of layers and the effect of underlying structure on the metrology signal  
The present invention includes a method and system for identifying an underlying structure that achieves improved planarization characteristics of layers while minimizing introduction of random...
7041513 Methods for forming semiconductor devices so as to stabilize the same when positioned face-down over test substrates  
One or more of stabilizers are disposed on the surface of a semiconductor device or test substrate that includes bond pads or contact pads located at or proximate to a centerline thereof prior to...
7036215 Method and program for obtaining positioning errors of printed-wiring board, and electronic-circuit-component mounting system  
An electronic-circuit-component mounting system including at least two component mounting units concurrently operated to mount electronic circuit components on a printed-wiring board, wherein a...
7033847 Determining the maximum number of dies fitting on a semiconductor wafer  
Determining the maximum number of dies that fit on a semiconductor wafer is disclosed. The x- and y-coordinates of an initial starting position on a semiconductor wafer are determined. The delta-x...
7031791 Method and system for a reject management protocol within a back-end integrated circuit manufacturing process  
A method and system for a reject management protocol within a back-end IC manufacturing process. In one method embodiment, the present invention implements a tracking process for a die-strip. The...
7026176 Mold making method for wafer scale caps  
Disclosed is a method for fabricating a mold. The mold is used for protective caps which will be applied to a wafer. The method comprises the steps of fabricating first and second cooperating mold...
7022533 Substrate mapping  
A method for fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having...
7023097 FBGA arrangement  
The invention relates to an FBGA arrangement, comprising a substrate on which at least one chip is chip-bonded face-down, which has a central row of bonding pads connected to contact islands...
7008825 Leadframe strip having enhanced testability  
A method of fabricating a semiconductor package comprising the step of providing a leadframe strip which defines a strip plane and a multiplicity of leadframes. Each of the leadframes includes an...
7005878 Method for in-line testing of flip-chip semiconductor assemblies  
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or...
6998701 Resin sealing-type semiconductor device and method for manufacturing the same  
A resin sealing-type semiconductor device comprises a first semiconductor chip 15 with a large amount of heat generation, whose external electrode leading-out bonding pads 16 are wire-bonded to...
6991947 Hybrid semiconductor circuit with programmable intraconnectivity  
Field programmable circuits and redundant logic are added to the substrate of a hybrid circuit with functionality to bypass and/or repair unusable dies in order to enhance yield and lower costs of...
6989334 Manufacturing method of a semiconductor device  
The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is...
6984533 Method of sorting dice by speed during die bond assembly and packaging to customer order  
When integrated circuit dice are tested as part of a completely manufactured wafer, the individual die is tested both for proper function and for speed grade. A wafer map is formed in a computer to...
6984532 Method of judging residual film by optical measurement  
A method of judging a residual film on a sample by an optical measurement, the sample including a first metal film whose reflectance is changed depending on a wavelength of measuring light, and an...
6972200 Method for manufacturing flip-chip semiconductor assembly  
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or...
6969623 Semiconductor device and method for manufacturing the same  
A semiconductor device and a method for manufacturing the semiconductor device mountable with high density, which includes a simplified process but is capable of reducing a defect rate. A plurality...
6969918 System for fabricating semiconductor components using mold cavities having runners configured to minimize venting  
A system for fabricating semiconductor components includes mating mold cavity plates having mold cavities configured to mold body segments of the semiconductor components on either side of a...
6968481 Method and device for adapting/tuning signal transit times on line systems or networks between integrated circuits  
A method and a device adapt/tune signal transit times on line systems or networks between integrated circuits which are mounted on printed circuit boards. Fine tuning of differences in transit...
6963193 a-C:H ISFET device, manufacturing method, and testing methods and apparatus thereof  
An a-C:H ISFET device and manufacturing method thereof. The present invention prepares a-C:H as the detection membrane of an ISFET by plasma enhanced low pressure chemical vapor deposition...
6963393 Measurement of lateral diffusion of diffused layers  
Any semiconductor wafer fabrication process may be changed to monitor lateral abruptness of doped layers as an additional step in the wafer fabrication process. In one embodiment, a test structure...
6946305 Apparatus for evaluating amount of charge, method for fabricating the same, and method for evaluating amount of charge  
A wafer for charge amount evaluation having a silicon substrate and p-type regions sandwiched between a first silicon oxide film and a SA-NSG film and surrounded by an undoped silicon film is...
6946306 Method of manufacturing a semiconductor device and a fabrication apparatus for a semiconductor device  
A method of manufacturing a semiconductor device able to reduce the number of manufacturing steps and attain the rationalization of a manufacturing line is disclosed. The semiconductor device is a...
6935922 Methods and systems for generating a two-dimensional map of a characteristic at relative or absolute locations of measurement spots on a specimen during polishing  
Methods and systems for generating a two-dimensional map of a characteristic at relative or absolute locations of measurement spots on a specimen during polishing are provided. One method includes...
6933610 Method of bonding a semiconductor die without an ESD circuit and a separate ESD circuit to an external lead, and a semiconductor device made thereby  
In a semiconductor device having a semiconductor die without an ESD circuit and a separate ESD circuit and an external lead, the external lead is first bonded to the separate ESD circuit....
6930323 Test keys structure for a control monitor wafer  
A test keys structure comprises a plurality of test keys in scribe lines of a control monitor wafer. Between 50 and 400 test keys are formed on the control monitor wafer, and each of the plurality...
6927079 Method for probing a semiconductor wafer  
A semiconductor wafer is placed into a probe fixture with a front side of the wafer facing up. Power and signal probes are then placed on an integrated circuit (IC) formed on the front side of the...
6927099 Process for producing semiconductor device and semiconductor device  
A process for producing a semiconductor device which comprises, in a process comprising mounting a semiconductor element in accordance with a flip chip bonding process, bonding the semiconductor...
6919228 Methods and apparatus for the detection of damaged regions on dielectric film or other portions of a die  
Techniques for detecting damage on an integrated circuit die using a particle suspension solution are disclosed. The particles of the suspension solution preferentially attach to damaged regions on...
6906404 Power module with voltage overshoot limiting  
A power module employs at least one capacitor electrically coupled across the input terminals to reduce voltage overshoot. The capacitor may be surface mounted to a high side collector plating area...
6900459 Apparatus for automatically positioning electronic dice within component packages  
A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the...
6897078 Programmable multi-chip module  
A multi-chip module comprising a low-temperature co-fired ceramic substrate having a first side on which are mounted active components and a second side on which are mounted passive components,...
6897076 Lithography system, exposure apparatus and their control method, and device manufacturing method  
A lithography system includes a pre-process apparatus which performs a pre-process for a substrate and an exposure apparatus which exposes the substrate pre-processed by the pre-process apparatus...
Matches 151 - 200 out of 726 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >