|
Match
|
Document |
Document Title |
|
|
6927079 |
Method for probing a semiconductor wafer
A semiconductor wafer is placed into a probe fixture with a front side of the wafer facing up. Power and signal probes are then placed on an integrated circuit (IC) formed on the front side of the...
|
|
|
6927081 |
Method of inkless wafer blind assembly
A method of blind assembly processing a wafer by pick and place equipment is described. This method includes determining the wafer diameter or radius and determining the bad die edge exclusive...
|
|
|
6927077 |
Method and apparatus for measuring contamination of a semiconductor substrate
An apparatus for measuring contamination of a semiconductor substrate includes a chuck for loading a substrate, a position detection means for recognizing a front surface of the loaded substrate to...
|
|
|
6927082 |
Method of evaluating the quality of a contact plug fill
Defective contact plug fills can be detected by applying an etching solution, which in some embodiments preferentially etches in the <111> direction. The etching solution is some embodiments...
|
|
|
6926935 |
Proximity deposition
The present invention provides methods for achieving substantially damage-free material deposition using charged particle (e.g., ion, electron) or light beams for generating secondary electrons to...
|
|
|
6925347 |
Process control based on an estimated process result
A method and apparatus is provided for a process control based on an estimated process result. The method comprises processing a workpiece using a processing tool, receiving trace data associated...
|
|
|
6925616 |
Method to test power distribution system
A method for testing a core power distribution system for an integrated circuit chip which includes arranging a plurality of experiments for an integrated circuit chip, performing the plurality of...
|
|
|
6921672 |
Test structures and methods for inspection of semiconductor integrated circuits
Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test...
|
|
|
6919214 |
Apparatus for analyzing a substrate employing a copper decoration
An apparatus for analyzing a substrate employing a copper decoration includes a bath having at least two receiving containers for receiving electrolytes, slots formed at insides of the receiving...
|
|
|
6918301 |
Methods and systems to detect defects in an end effector for conditioning polishing pads used in polishing micro-device workpieces
Methods and systems to detect defects in an end effector for conditioning polishing pads used in polishing micro-device workpieces are disclosed herein. In one embodiment, a method of detecting...
|
|
|
6916657 |
Evaluation method for polycrystalline silicon
An evaluation method for polycrystalline silicon including the steps of immersing the polycrystalline silicon in an agent which is capable of dissolving the polycrystalline silicon, and counting...
|
|
|
6916671 |
Gate oxide measurement apparatus
An apparatus for measuring a gate oxide thickness comprises a first active area, first to fifth wordlines, first and second bar-shaped trench capacitors, and first and second gate structures. The...
|
|
|
6912778 |
Methods of fabricating full-wafer silicon probe cards for burn-in and testing of semiconductor devices
A full-wafer probe card, a method for making the probe card and a full-wafer testing system are provided. The probe card includes test probes comprising cantilever elements configured and arranged...
|
|
|
6915177 |
Comprehensive integrated lithographic process control system based on product design and yield feedback system
The present invention provides systems and methods that facilitate performing fabrication process. Critical parameters are valued collectively as a quality matrix, which weights respective...
|
|
|
6911349 |
Evaluating sidewall coverage in a semiconductor wafer
A sidewall or other feature in a semiconductor wafer is evaluated by illuminating the wafer with at least one beam of electromagnetic radiation, and measuring intensity of a portion of the beam...
|
|
|
6911157 |
Plasma processing method and apparatus using dynamic sensing of a plasma environment
At least one control parameter such as power supplied to a plasma, process pressure, gas flow rate, and radio frequency bias power to a wafer is changed for an extremely short time as compared with...
|
|
|
6908773 |
ATR-FTIR metal surface cleanliness monitoring
Attenuated total reflectance (ATR)-Fourier transform infrared (FTIR) metal surface cleanliness monitoring is disclosed. A metal surface of a semiconductor die is impinged with an infrared (IR)...
|
|
|
6908775 |
Method for performing an alignment measurement of two patterns in different layers on a semiconductor wafer
In an alignment or overlay measurement of patterns on a semiconductor wafer an error that occurs during the measurement in one of a predefined number of alignment structures in an exposure field of...
|
|
|
6908774 |
Method and apparatus for adjusting the thickness of a thin layer of semiconductor material
A method for adjusting the thickness of a thin semiconductor material layer. The method includes measuring the layer to establish a thickness profile, determining thickness adjustment...
|
|
|
6905966 |
METHOD FOR ESTIMATING REMAINING FILM THICKNESS DISTRIBUTION, METHOD FOR DESIGNING PATTERNING MASK USING THE METHOD FOR ESTIMATING REMAINING FILM THICKNESS DISTRIBUTION, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES BY USING PATTERNING MASK DESIGNED BY USING THE METHOD FOR ESTIMATING REMAINING FILM THICKNESS DISTRIBUTION
A method for estimating relative remaining film thickness distribution (CMP pattern ratio distribution) among sparse and dense active regions after CMP on the basis of the layout of a mask pattern...
|
|
|
6905893 |
Method and structure for determining a concentration profile of an impurity within a semiconductor layer
A method is provided for determining a concentration profile of an impurity within a layer of a semiconductor topography. The method may include exposing the layer and an underlying layer to...
|
|
|
6906341 |
Probe needle test apparatus and method
A test apparatus is provided which includes a substrate retainer, a probe card, a tester, a test head, and a main controller. The substrate retainer is for holding a substrate having a plurality of...
|
|
|
6905892 |
Operating method for a semiconductor component
The present invention creates an operating method for a semiconductor component having a substrate; having a conductive polysilicon strip which is applied to the substrate; having a first and a...
|
|
|
6905891 |
Method for processing multiple semiconductor devices for test
A packaged array ( 10 ) having a temporary substrate ( 20 ) is used to test a plurality of semiconductor devices ( 14 ). In one embodiment, the temporary substrate ( 20 ) is an adhesive substrate,...
|
|
|
6902941 |
Probing of device elements
A new and improved method for the probing of integrated circuits (ICs) and is particularly suitable for probing various elements of an IC for failure analysis or other electrical testing and/or...
|
|
|
6901342 |
Test wafer usage forecast modeling method
A method for modeling usage of semiconductor test wafers comprises the steps of: calculating an individual demand for test wafers by each of a plurality of tools, assigning respective ones of the...
|
|
|
6900135 |
Buffer station for wafer backside cleaning and inspection
A wafer processing station includes an air gap chuck and a light emitter/collector assembly configured to gather light when scattered or reflected by contaminants on the wafer. The light...
|
|
|
6900065 |
Apparatus and method for enhanced voltage contrast analysis
An apparatus and a method for electrically testing a semiconductor wafer, the method including: (i) depositing electrical charges at certain points of a test pattern; (ii) scanning at least a...
|
|
|
6897077 |
Test structure for determining a short circuit between trench capacitors in a memory cell array
A test structure allows determining a short circuit between trench capacitors in a memory cell array in which the trench capacitors are arranged in matrix form. The test structure has, in two rows...
|
|
|
6897076 |
Lithography system, exposure apparatus and their control method, and device manufacturing method
A lithography system includes a pre-process apparatus which performs a pre-process for a substrate and an exposure apparatus which exposes the substrate pre-processed by the pre-process apparatus...
|
|
|
6897475 |
Test structure and related methods for evaluating stress-induced voiding
This disclosure provides, in one aspect, a test structure formed within a semiconductor wafer. In one embodiment, the test structure comprises a plurality of first level bulk metals having varying...
|
|
|
6898558 |
Method and apparatus for monitoring a material processing system
The present invention presents an apparatus and method for monitoring a material processing system, wherein the material processing system includes a processing tool, a number of RF-responsive...
|
|
|
6895295 |
Method and apparatus for controlling a multi-chamber processing tool
A method for controlling a processing tool having a plurality of chambers includes processing a wafer in a first chamber of the processing tool; measuring a characteristic of the wafer; and...
|
|
|
6893884 |
Method and apparatus for measuring dopant profile of a semiconductor
A method and apparatus for measuring dopant profile of a semiconductor is disclosed. Initially, the temperature of a tip of a probe and the temperature of a semiconductor sample are ascertained....
|
|
|
6893883 |
Method and apparatus using an on-chip ring oscillator for chip identification
An apparatus and method for identifying integrated circuit chips or dice on a semiconductor wafer. Each chip comprises a ring oscillator having a characteristic oscillating frequency different from...
|
|
|
6893882 |
Multivariate RBR tool aging detector
A multiple run by run process is described. A plurality of tools and a plurality of products to be run on the tools are provided. Tool effects and product effects on a parameter are identified for...
|
|
|
6890773 |
Dynamic maintenance of manufacturing system components
A method and an apparatus for sorting between actual and perceived errors related to processing of semiconductor wafers. A plurality of semiconductor wafers are processed. Fault data relating to...
|
|
|
6890775 |
Yield based, in-line defect sampling method
A test method provides a sample of wafer level defects most likely to cause yield loss on a semiconductor wafer subdivided into a plurality of integrated circuits (ICs). Defect size and location...
|
|
|
6890776 |
Silicon oxide film evaluation method and semiconductor device fabrication method
A silicon oxide film formed on a compound semiconductor substrate is evaluated by estimating the quantity of silicon-silicon bonds operating as electron traps in the silicon oxide film from a peak...
|
|
|
6890774 |
System and method for creating a substrate signature
The present invention is a system for creating a signature of a substrate manufactured in a semiconductor or data storage fabrication facility. A central processing unit is configured to receive...
|
|
|
6890772 |
Method and apparatus for determining two dimensional doping profiles with SIMS
A method of forming a SIMS monitor device for determining a doping profile of a semiconductor device structure including providing a plurality of regularly repeating semiconductor structures...
|
|
|
6887723 |
Method for processing an integrated circuit including placing dice into a carrier and testing
Methods for processing at least one die which comprises an integrated circuit. In one example of a method of the invention, an identification code is applied to a carrier. A singulated die is...
|
|
|
6884146 |
Systems and methods for characterizing a polishing process
Systems and methods for characterizing a polishing process are provided. One method includes scanning a specimen with two or more measurement devices during polishing. In one embodiment, the two or...
|
|
|
6884639 |
Semiconductor wafer pod
A semiconductor wafer pod includes a measurement sensor configured within a housing. The sensor faces towards a surface of a wafer being accommodated in the pod. The pod can be connected to the...
|
|
|
6885466 |
Method for measuring thickness of oxide film
In a process of manufacturing a semiconductor device, after a gate oxide film is formed, the thickness of the gate oxide film is measured by measuring an exposure period defined from a time at...
|
|
|
6884641 |
Site-specific methodology for localization and analyzing junction defects in mosfet devices
This invention relates to a method for electrically localizing site-specific defective sub 130 nm node MOSFET devices with shallow (less than 80 nm deep) source/drain junctions utilizing bulk...
|
|
|
6884638 |
METHOD OF FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE BY DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING AN OVERDRIVE CURRENT MEASUREMENT TECHNIQUE AND A DEVICE THEREBY FABRICATED
A method for fabricating a flash memory device by determining the active region width ( 10 ) of a semiconductor device ( 27 ) using a measuring technique for the source drain overdrive current...
|
|
|
6885955 |
Semiconductor process yield analysis based on evaluation of parametric relationship
Semiconductor process yield analysis in which the relationship between a wafer-level parameter and a die-level parameter is evaluated can be performed more quickly and with greater accuracy than...
|
|
|
6884640 |
Method and apparatus for determining layer thickness and composition using ellipsometric evaluation
One embodiment of the present invention provides a system that determines the composition of a layer within an integrated device. The system operates by first receiving the integrated device. Next,...
|
|
|
6884642 |
Wafer-level testing apparatus and method
A semiconductor component configured for wafer-level testing includes a semiconductor die having at least one die contact electrically exposed for coupling with a redistribution circuit that...
|