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RE38900 |
Automating photolithography in the fabrication of integrated circuits
Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography...
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6969620 |
Semiconductor device inspection system
A device inspection apparatus inspects a plurality of semiconductor devices on an individual device basis. An inspection target sorting part ( 8 ) omits an execution of an inspection to be applied...
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6969619 |
Full spectrum endpoint detection
A method of endpoint detection during plasma processing of a semiconductor wafer comprises processing a semiconductor wafer using a plasma, detecting radiation emission from the plasma during the...
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6969621 |
Contamination distribution apparatus and method
Embodiments of the invention include an apparatus for uniformly contaminating samples. The apparatus includes a housing that contains a rotatable carousel for the holding samples. A drive element...
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6968481 |
Method and device for adapting/tuning signal transit times on line systems or networks between integrated circuits
A method and a device adapt/tune signal transit times on line systems or networks between integrated circuits which are mounted on printed circuit boards. Fine tuning of differences in transit...
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6967112 |
Three-dimensional quantum dot structure for infrared photodetection
A 3D quantum dot optical path structure is provided, along with a method for selectively forming a 3D quantum dot optical path. The method comprises: forming a single crystal Si substrate with a...
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6968287 |
System and method for predicting burn-in conditions
According to one embodiment of the invention, a method for predicting burn-in conditions includes identifying a baseline IDDQ, a baseline temperature, and a baseline IDDQ current density based on a...
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6964875 |
Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance
Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric...
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6964874 |
Void formation monitoring in a damascene process
The invention provides a technique of monitoring the void formation in a damascene interconnection process. According to the invention, a test structure is provided that includes at least two...
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6963082 |
Multi-chip package device including a semiconductor memory chip
A multi-chip package device includes package terminals, a semiconductor memory chip and an interface chip. The semiconductor memory chip has a test circuit and a test terminal. The test circuit is...
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6962827 |
Semiconductor device capable of shortening test time and suppressing increase in chip area, and method of manufacturing semiconductor integrated circuit device
A plurality of semiconductor integrated circuits and a plurality of TEG circuits are aligned and provided on a substrate. In the TEG circuit, a built-in test circuit is provided in a region which...
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6963193 |
a-C:H ISFET device, manufacturing method, and testing methods and apparatus thereof
An a-C:H ISFET device and manufacturing method thereof. The present invention prepares a-C:H as the detection membrane of an ISFET by plasma enhanced low pressure chemical vapor deposition...
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6963393 |
Measurement of lateral diffusion of diffused layers
Any semiconductor wafer fabrication process may be changed to monitor lateral abruptness of doped layers as an additional step in the wafer fabrication process. In one embodiment, a test structure...
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6960802 |
Performing passive voltage contrast on a silicon on insulator semiconductor device
A method and type of device for performing passive voltage contrast on a silicon on insulator (SOI) device. A first portion of a substrate of the SOI device may be ground with a dimpler. A second...
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6960123 |
Cleaning sheet for probe needles
A cleaning sheet has a disc-shaped substrate. First and second polishing layers are disposed over the substrate. The first polishing layer has a surface formed in a surface-roughened fashion to...
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6958248 |
Method and apparatus for the improvement of material/voltage contrast
A method and system for registering a CAD layout to a Focused Ion Beam image for through-the substrate probing, without using an optical image and without requiring biasing, includes an improved...
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6957581 |
Acoustic detection of mechanically induced circuit damage
An apparatus and method thereof includes at least one acoustic transducer for receiving acoustic emissions produced during a semiconductor fabrication process. The acoustic transducer is mounted to...
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6959252 |
Method for analyzing in-line QC test parameters
A method for analyzing in-line QCtest parameters is used to analyze a plurality of lots of products, each lot of products having a lot number and being formed using a plurality of equipments. At...
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6957120 |
Multi-level process data representation
A method and an apparatus for implementing enhancing data population based upon manufacturing data. A first and a second workpiece are processed. Metrology data relating to the first workpiece is...
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6955929 |
Method of measuring a gate channel length of a metal-oxide semiconductor transistor
A predetermined voltage is applied respectively on a first gate of a first metal-oxide semiconductor (MOS) transistor with a known channel length and a second gate of a second MOS transistor with...
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6955987 |
Comparison of chemical-mechanical polishing processes
Chemical-mechanical polishing (“CMP”) processes performed on bodies ( 10 ), each having areas ( 16 and 18 ) of different depression pattern densities, are compared by correlating polishing...
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6955928 |
Closed loop residual gas analyzer process control technique
A technique for use in fabricating an integrated circuit are disclosed. The method generally begins by performing an operation on a wafer using a fabrication tool. Next, volatiles are desorbed from...
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6955930 |
Method for determining thickness of a semiconductor substrate at the floor of a trench
Apparatus and method for exposing a selected feature of an integrated circuit device such as a selected portion of the metallization layer, from the backside of the integrated circuit substrate...
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6953755 |
Technique for monitoring the state of metal lines in microstructures
By preparing fully-embedded interconnect structure samples for a cross-section analysis by means of electron microscopy or x-ray microscopy, degradation mechanisms may be efficiently monitored....
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6954678 |
Artificial intelligence system for track defect problem solving
A system and method facilitating lithography defect solution generation is provided. The invention includes a defect solution component and a defect alert component. The defect solution component...
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6951767 |
Development hastened stability of titanium nitride for APM etching rate monitor
A method of fabricating a stabilized TiN control wafer comprising the following steps. A silicon substrate is provided having a silicon oxide layer formed thereover. An initial TiN layer is formed...
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6951765 |
Method and apparatus for introduction of solid precursors and reactants into a supercritical fluid reactor
The present invention pertains to apparatus and methods for introduction of solid precursors and reactants into a supercritical fluid reactor. Solids are dissolved in supercritical fluid solvents...
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6949387 |
Method of designing a semiconductor device
A technique for a semiconductor device is provided that includes forming circuit regions on a device formation region and device isolation regions on a semiconductor substrate, a ratio of the width...
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6946304 |
Apparatus for and method of manufacturing a semiconductor device, and cleaning method for use in the apparatus for manufacturing a semiconductor device
An apparatus for manufacturing a semiconductor device, comprising a process chamber which holds a substrate to be subjected to a prescribed process, a gas inlet pipe which introduces a process gas...
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6946305 |
Apparatus for evaluating amount of charge, method for fabricating the same, and method for evaluating amount of charge
A wafer for charge amount evaluation having a silicon substrate and p-type regions sandwiched between a first silicon oxide film and a SA-NSG film and surrounded by an undoped silicon film is...
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6946303 |
Electronically diagnosing a component in a process line using a substrate signature
The present invention is a system for creating a signature of a substrate manufactured in a semiconductor or data storage fabrication facility. A central processing unit is configured to receive...
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6946378 |
Methods for fabricating protective structures for bond wires
A method for fabricating a protective structure for bond wires of a semiconductor device assembly which includes sequentially fabricating one or more layers of the protective structure. After a...
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6946394 |
Methods and systems for determining a characteristic of a layer formed on a specimen by a deposition process
Methods and systems for monitoring semiconductor fabrication processes are provided. A system may include a stage configured to support a specimen and coupled to a measurement device. The...
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6943055 |
Method and apparatus for detecting backside contamination during fabrication of a semiconductor wafer
A method of detecting contamination on a backside of a semiconductor wafer includes the steps of positioning the backside of the wafer in contact with a detection surface of a contaminant sensor,...
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6943043 |
Surface contamination analyzer for semiconductor wafers, method used therein and process for fabricating semiconductor device
A semiconductor wafer is radiated with an electron beam so that the inelastic scattering takes place in the narrow region, and current flows out from the narrow region; the amount of current is...
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6943042 |
Method of detecting spatially correlated variations in a parameter of an integrated circuit die
A method of detecting spatially correlated variations that may be used for detecting statistical outliers in a production lot of integrated circuits to increase the average service life of the...
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6943108 |
Interposer capacitor built on silicon wafer and joined to a ceramic substrate
An interposer, located between an integrated circuit having power, ground and signal connections and a ceramic substrate having power, ground and signal connections, that includes an oxide layer...
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6938505 |
Chamber wafer detection
An apparatus and method for detecting in chamber wafer position and process status are disclosed. A chamber includes a processing pedestal and plurality of lift pins. Each lift pin has an...
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6939726 |
Via array monitor and method of monitoring induced electrical charging
An electrical monitor comprising a via array and method for determining and reducing an electrically charged state of a semiconductor process wafer the method including providing a metal filled via...
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6939472 |
Etching method in fabrications of microstructures
The present invention teaches a method and apparatus for removing sacrificial materials in fabrications of microstructures using one or more selected spontaneous vapor phase etchants. The selected...
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6939727 |
Method for performing statistical post processing in semiconductor manufacturing using ID cells
A method of manufacturing a semiconductor integrated circuit includes providing a fabricated integrated circuit on a wafer. A test fixture is connected to unencapsulated pads on the integrated...
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6939794 |
Boron-doped amorphous carbon film for use as a hard etch mask during the formation of a semiconductor device
A hard mask comprising boron-doped amorphous carbon, and a method for forming the hard mask, provides improved resistance to etches of a variety of materials compared with previous amorphous carbon...
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6936904 |
Photo sensing integrated circuit device and related circuit adjustment
A light-receiving element having a light-receiving portion is formed on a chip surface. A digital circuit element, an analog circuit element and a circuit adjusting element are provided for...
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6935922 |
Methods and systems for generating a two-dimensional map of a characteristic at relative or absolute locations of measurement spots on a specimen during polishing
Methods and systems for generating a two-dimensional map of a characteristic at relative or absolute locations of measurement spots on a specimen during polishing are provided. One method includes...
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6936483 |
On-wafer burn-in of semiconductor devices using thermal rollover
Apparatus and method for on-wafer burn-in of a semiconductor device. In a preferred embodiment, the present invention is realized using an auto-prober commonly used in scan-testing of semiconductor...
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6936480 |
Method of controlling the chemical mechanical polishing of stacked layers having a surface topology
An improved CMP controller allows the calculation of the polish time required for removing a patterned layer stack to a desired final thickness, wherein the initial layer thickness of each layer...
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6933610 |
Method of bonding a semiconductor die without an ESD circuit and a separate ESD circuit to an external lead, and a semiconductor device made thereby
In a semiconductor device having a semiconductor die without an ESD circuit and a separate ESD circuit and an external lead, the external lead is first bonded to the separate ESD circuit....
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6930382 |
Semiconductor device and method of manufacturing the same
A semiconductor device includes a first substrate including an element, a first plug penetrating through the first substrate, made of a conductive material, and electrically connected with the...
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6929965 |
Early response to plasma/charging damage by special pattern design of active region
A method of early and effective detection of plasma damage to a gate oxide layer by a special design of the active region is achieved. A plasma-damage testing structure is fabricated by providing a...
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6927080 |
Structures for analyzing electromigration, and methods of using same
The present invention is generally directed to various structures for analyzing electromigration, and methods of using same. In one illustrative embodiment, the method includes forming a grating...
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