Matches 1 - 50 out of 137 1 2 3 >
Match Document Document Title
7618850 Method of making a diode read/write memory cell in a programmed state  
A method of making a nonvolatile memory device includes fabricating a diode in a low resistivity, programmed state without an electrical programming step. The memory device includes at least one...
7572682 Semiconductor structure for fuse and anti-fuse applications  
A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin...
7566594 Fabricating method of semiconductor device  
A fuse region and a wiring region are defined on a base to form a fuse in the fuse region of the base. A first insulation film is formed on the base and the fuse. After a first contact opening is...
7550789 Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable  
Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided....
7531388 Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabricating thereof  
Electrically programmable fuse structures and methods of fabrication thereof are presented, wherein a fuse includes first and second terminal portions interconnected by an elongate fuse element....
7488624 Techniques for providing decoupling capacitance  
Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias...
7485559 Semiconductor device and method of fabricating the same  
A semiconductor device and methods thereof. The semiconductor device includes a first layer formed on a substrate, the first layer having a higher conductivity. The semiconductor device further...
7447273 Redundancy structure and method for high-speed serial link  
An integrated circuit is provided having a plurality of data transmitters, including a plurality of default data transmitters for transmitting data from a plurality of data sources and at least one...
7442605 Resistively switching memory  
The present invention relates to a reproducible conditioning during the manufacturing of a resistively switching CBRAM memory cell comprising a first electrode and a second electrode with an active...
7429503 Method of manufacturing well pick-up structure of non-volatile memory  
A method of manufacturing a well pick-up structure of a non-volatile memory is provided. A substrate including a first conductive type well, device isolation structures and dummy memory columns is...
7425471 Semiconductor structure processing using multiple laser beam spots spaced on-axis with cross-axis offset  
Methods and systems selectively irradiate structures on or within a semiconductor substrate using a plurality of laser beams. The structures are arranged in a row extending in a generally...
7364951 Nonvolatile semiconductor memory device and method for manufacturing the same  
A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell...
7348263 Manufacturing method for electronic component, electronic component, and electronic equipment  
A manufacturing method for electronic device, includes: preparing a first substrate having a plurality of first regions; preparing a second substrate having a plurality of second regions; facing...
7332379 Method of an array of structures sensitive to ESD and structure made therefrom  
A method of fabricating an array of structures sensitive to ESD is disclosed. First, an array of structures is provided on a substrate, with the structures conductively coupled by interconnections....
7300825 Customizing back end of the line interconnects  
Custom connections between pairs of copper wires in a last damascene wiring level are effected by creating openings in an overlying insulating layer which span a distance between portions of the...
7208350 Method and device for producing layout patterns of a semiconductor device having an even wafer surface  
Primitive cells, which are circuit patterns of the constituent elements of a semiconductor device, are arranged in the element formation area of a semiconductor device, and at least one fill cell...
7186571 Method of fabricating a compositionally modulated electrode in a magnetic tunnel junction device  
A magnetic tunnel junction device with a compositionally modulated electrode and a method of fabricating a magnetic tunnel junction device with a compositionally modulated electrode are disclosed....
7176535 Thin film transistor array gate electrode for liquid crystal display device  
The present invention discloses a TFT array substrate that is fabricated using a four-mask process and a method of manufacturing that TFT array substrate. The gate line and gate electrode of the...
7141995 Semiconductor manufacturing device and semiconductor manufacturing method  
A semiconductor manufacturing device includes a prober whose needles are at once engaged for contacting pads of two chip forming regions within a wafer. In one chip forming region, trimming is...
7105877 Conductive line structure  
A conductive line Structure. In one embodiment of the invention, a conductive line includes at least two outer conductive portions, an inner conductive portion between the outer conductive...
7075140 Low voltage EEPROM memory arrays  
A non-volatile memory array includes memory cells connected in a common source arrangement and formed in columns of isolated well regions so that Fowler-Nordheim tunneling is used for both write...
7042079 Variable rotational assignment of interconnect levels in integrated circuit fabrication  
Integrated circuit fabrication techniques are provided which allow non-horizontal/non-vertical wires to traverse the entire chip surface, rather than just the corners as in the conventional...
7029956 Memory system capable of operating at high temperatures and method for fabricating the same  
A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a...
6989307 Mask ROM, and fabrication method thereof  
The present invention discloses a mask ROM which has excellent compatibility with a logic process and improves integration of a memory cell, and a fabrication method thereof. The mask ROM includes:...
6972217 Low k polymer E-beam printable mechanical support  
A low-k interconnect dielectric layer is strengthened by forming pillars of hardened material in the low-k film. An E-beam source is used to expose a plurality of pillar locations. The locations...
6969642 Method of controlling implantation dosages during coding of read-only memory devices  
A method of controlling implantation dosages during coding of read-only memory (ROM) devices is disclosed. According to the method, a semi-manufactured ROM device having a plurality of gates with...
6955926 Method of fabricating data tracks for use in a magnetic shift register memory device  
A magnetic data track used in a magnetic shift register memory system may be fabricated by forming a multilayered stack of alternating dielectric and/or silicon layers. Vias of approximately 10...
6949423 MOSFET-fused nonvolatile read-only memory cell (MOFROM)  
With directly biasing drain to source in a floating-gate N-MOSFET, a new MOSFET-fused nonvolatile ROM cell (MOFROM) is provided by tunneling-induced punch through of the drain junction to the...
6949416 Method of manufacturing a semiconductor integrated circuit device  
Disclosed is a technique capable of enhancing the degree of freedom in the layout of a rerouting layer in a wafer level CSP in which defect repairing is performed by cutting a fuse. More...
6946330 Designing method and manufacturing method for semiconductor display device  
Irrespective of a specification of the controller, a plurality of TFTs are formed for the controller on a substrate in advance. Then, in accordance with a design of the controller, connection is...
6887804 Passivation processing over a memory link  
A set ( 50 ) of one or more laser pulses ( 52 ) is employed to remove passivation layer ( 44 ) over a conductive link ( 22 ). The link ( 22 ) can subsequently be removed by a different process such...
6864123 Memory device and manufacturing method therefor  
A technique for manufacturing memory devices which can easily manufacture ROM semiconductors having various write patterns at lower cost in a short period of time is disclosed. Since a simple...
6818481 Method to manufacture a buried electrode PCRAM cell  
An exemplary embodiment of the present invention includes a method for forming a programmable cell by forming an opening in a dielectric material to expose a portion of an underlying first...
6797545 Method and apparatus for fabricating electronic device  
Logic circuitry formed in street areas between adjacent fabricated electronic devices may be used as auxiliary or redundant components to salvage one or more otherwise defective devices. Logic...
6794201 Method of fabricating semiconductor device  
A method of fabricating a semiconductor device characterized in that the method includes the steps of forming basic structures of unit FETs on each of ‘m’ active layer regions more than the...
6777269 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, DESIGN METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, DESIGN AIDING DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, PROGRAM, AND PROGRAM RECORDING MEDIUM  
A first signal path of a circuit 300 of the present invention is formed by connecting a restricted area 331 in the electrically disconnected state, restricted areas 321 and 311 in the...
6737726 Resistance variable device, analog memory device, and programmable memory cell  
In one implementation, a non-volatile resistance variable device includes a body formed of a voltage or current controlled resistance setable material, and at least two spaced electrodes on the...
6720212 Method of eliminating back-end rerouting in ball grid array packaging  
Disclosed is a method of ball grid array packaging, comprising the steps of providing a semiconductor die having a metal conductors thereon, covering said metal conductors with an insulative layer,...
6720210 Mask ROM structure and manufacturing method thereof  
A mask read-only-memory structure and its method of manufacture are provided. The structure includes a substrate, a buried bit line in the substrate and a patterned stack layer covering a portion...
6703651 Electronic device having stacked modules and method for producing it  
An electronic device having stacked modules and method for producing it are described. Each module has a chip. Each chip is mounted on a stack intermediate plane. The stack intermediate planes of a...
6700142 Semiconductor wafer on which is fabricated an integrated circuit including an array of discrete functional modules  
The present invention provides a semiconductor wafer that has a predetermined global functionality and comprises a top surface, a bottom surface and a peripheral edge between the top surface and...
6692995 Physically deposited layer to electrically connect circuit edit connection targets  
Disclosed is a layer to electrically connect targets during a circuit edit of an integrated circuit and systems and methods for forming the layer. The layer contains a conductive material, such as...
6682959 Architecture of laser fuse box of semiconductor integrated circuit and method for fabricating the same  
The invention relates to a fuse layout structure in a laser fuse box of a semiconductor integrated circuit and a method for fabricating the same. In one example of the invention, the fuse layout...
6674132 Memory cell and production method  
A memory cell, which is isolated from other memory cells by STI trenches, each includes an ONO layer structure between a gate electrode and a channel region formed in a semiconductor body. The gate...
6642587 High density ROM architecture  
A ROM array which provides for reduced size and power consumption. The bit cell of the ROM provides that a first type of information is stored in the bit cell when a transistor is disposed between...
6638820 Method of forming chalcogenide comprising devices, method of precluding diffusion of a metal into adjacent chalcogenide material, and chalcogenide comprising devices  
A method of precluding diffusion of a metal into adjacent chalcogenide material upon exposure to a quanta of actinic energy capable of causing diffusion of the metal into the chalcogenide material...
6613611 ASIC routing architecture with variable number of custom masks  
A customizable ASIC routing architecture is provided. The architecture utilizes the uppermost metal layers of an ASIC composed of an array of function blocks for routing among function blocks while...
6613604 Method for making small pore for use in programmable resistance memory element  
A method for making a small pore. The defined pore is useful for the fabrication of programmable resistance memory elements. The programmable resistance memory material may be a chalcogenide.
6603219 Semiconductor integrated circuit  
A semiconductor integrated circuit includes a plurality of units. Each of the units includes a power supply pad, a function circuit, and a power supply control circuit. The plurality of units each...
6586815 Semiconductor device having dummy interconnection and method for manufacturing the same  
A semiconductor device having an array of dummy interconnections in a fuse window are proposed. The each dummy interconnection comprised of a fuse body scheduled to be blown away by laser beam, a...
Matches 1 - 50 out of 137 1 2 3 >