Matches 1 - 50 out of 364 1 2 3 4 5 6 7 8 >


Match Document Document Title
8183554 Symmetrical programmable memresistor crossbar structure  
A crossbar structure includes a first layer or layers including first p-type regions and first n-type regions, a second layer or layers including second p-type regions and second n-type regions,...
8178905 Layout structure of semiconductor device  
In a layout structure capable of independent supply of a substrate or well potential from a power supply potential, further reduction in layout area is achieved. A reinforcing power supply cell is...
8173491 Standard cell architecture and methods with variable design rules  
Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a...
8168479 Resistance variable memory device and method of fabricating the same  
A method of fabricating a resistance variable device includes forming selection devices on a substrate, forming a conductive layer on the selection devices, patterning the conductive layer in a...
8168478 Method for producing a matrix of individual electronic components and matrix produced thereby  
The invention relates to a method for producing a matrix of electronic components, comprising a step of producing an active layer on a substrate, and a step of individualizing the components by...
8163614 Method for forming NAND typed memory device  
A method for fabricating a NAND type flash memory device includes defining a select transistor region and a memory cell region in a semiconductor substrate, forming a tunnel insulating layer, a...
8150315 Method for verifying the alignment between integrated electronic devices  
A method for verifying alignment between first and second integrated devices coupled together using a reference and a coupling capacitor, including: transmitting a reference signal on a...
8145851 Integrated device  
An integrated device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory...
8143152 Manufacturing method of semiconductor device having self-aligned contact connected to silicide layer on substrate surface  
A semiconductor device 100 includes: a silicon substrate 102; a first gate 114a including a gate electrode 108 formed on the silicon substrate 102 and sidewalls 112 formed on the sidewalls of the...
8145341 Product based configuration and control of manufacturing equipment  
Methods and apparatus, including computer program products, for product based configuration and control of manufacturing equipment. The present invention provides a method for manufacturing. The...
8133765 Integrated RF ESD protection for high frequency circuits  
The invention relates to a high-frequency integrated circuit requiring ESD protection for a circuit node. One or more metallic layer is deposited within the integrated circuit and patterned to form...
8136070 Shallow trench isolation dummy pattern and layout method using the same  
A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a...
8129221 Semiconductor package and method of forming the same  
Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first...
8105885 Hardened programmable devices  
Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used...
8102456 CCD array with integrated high voltage protection circuit  
A CCD containing circuit and method for making the same. The circuit includes a CCD array and a protection circuit. The CCD array is constructed on an integrated circuit substrate and includes a...
8097498 Damascene method of making a nonvolatile memory device  
A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device...
8084303 Semiconductor device and a method of manufacturing the same  
In a memory cell array on a main surface of a semiconductor substrate, a floating gate electrode for accumulating charges for information is arranged. The floating gate electrode is covered with a...
8067295 Manufacturing method of solar cell module, and solar cell and solar cell module  
A double-side light receiving solar cell in a planer regular hexagon shape and having first electrodes on both surfaces are divided into four pieces by a line A-A′ connecting two opposing apexes a...
8062944 Method for fabricating non-volatile storage with individually controllable shield plates between storage elements  
A method for fabricating non-volatile storage having individually controllable shield plates between storage elements. The shield plates are formed by depositing a conductive material such as doped...
8058656 Method for producing a matrix of individual electronic components and matrix produced thereby  
The invention relates to a method for producing a matrix of electronic components, comprising a step of producing an active layer on a substrate, and a step of individualizing the components by...
8043900 Semiconductor integrated circuit device and a method of manufacturing the same  
To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. In order to prevent noise from a power supply potential...
8034668 Method for forming semiconductor device having metallization comprising select lines, bit lines and word lines  
A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the...
8030733 Copper-compatible fuse target  
A copper-compatible fuse target is fabricated by forming a copper target structure at the same time that the copper traces are formed. After the copper target structure and the copper traces have...
8026585 Die stacking structure and fabricating method thereof  
A layout structure and layout method are provided. The layout structure includes a first conductive via, a second conductive via, a die and eight pads. The first conductive via and the second...
8021897 Methods of fabricating a cross point memory array  
Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal direction, a multi-sided container of access...
8021933 Integrated circuit including structures arranged at different densities and method of forming the same  
A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which are arranged more densely than the...
8012811 Methods of forming features in integrated circuits  
A feature is formed in an integrated circuit by providing one or more layers to be patterned, providing a first layer overlying the one or more layers to be patterned, and providing a second layer...
8003984 Reticle for wafer test structure areas  
Techniques are provided for forming die on wafers with large area test structures between primary die. A reticle is used to pattern each die. The pattern on the reticle forms a primary die and test...
7994068 Method for fabricating a 3-D integrated circuit using a hard mask of silicon-oxynitride on amorphous carbon  
A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide,...
7989963 Transistor circuit formation substrate  
A specially designed mask controls the arrangement of conductive materials that form a source and drain of a transistor. Designing the mask can be costly and time-consuming, which means that the...
7985990 Transistor layout for manufacturing process control  
A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first...
7986163 Scalable non-blocking switching network for programmable logic  
A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors...
7968882 Flexible display device and manufacturing method thereof  
A flexible display device adapted to prevent a disconnection of pad electrode and a line short-circuit is disclosed. The flexible display device and the manufacturing method thereof according to...
7960767 System for programmable gate array with sensor array  
The present invention provides providing a substrate, forming a sensor array on the substrate, forming a structured array of uncommitted logic surrounding the sensor array on the substrate, and...
7951652 Mask layout method, and semiconductor device and method for fabricating the same  
Provided are a mask layout method and a semiconductor device and a method for fabricating the same. The semiconductor device can include a main pattern, a first dummy pattern, and a second dummy...
7943436 Integrated circuit devices and methods and apparatuses for designing integrated circuit devices  
Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment of the present invention, a shielding mesh of at least two reference voltages...
7939384 Eliminating poly uni-direction line-end shortening using second cut  
A method of forming an integrated circuit structure includes providing a substrate including a first active region and a second active region; forming a gate electrode layer over the substrate; and...
7936071 Semiconductor device having a specified terminal layout pattern  
A semiconductor device comprises a semiconductor substrate that is provided with an integrated circuit; a multi-layered member that is installed in the semiconductor substrate, including a...
7927926 Non-volatile semiconductor storage device and method of manufacturing the same  
A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprises: a...
7915092 Nonvolatile memory with a unified cell structure  
A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E...
7910407 Quad memory cell and method of making same  
A non-volatile memory device includes a first electrode, a diode steering element, at least three resistivity switching storage elements, and a second electrode. The diode steering element...
7911551 Liquid crystal display device and fabrication method thereof  
A method for fabricating a display includes providing a first substrate divided into a pixel part and first and second pad parts, forming a gate electrode and a gate line in the pixel part of the...
7902880 Transitioning digital integrated circuit from standby mode to active mode via backgate charge transfer  
Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate,...
7901999 FPGA equivalent input and output grid muxing on structural ASIC memory  
The present invention provide circuits, methods, and apparatus directed to an integrated circuit having a memory interface that is configurable to have one of a multiple different bus widths. The...
7897499 Method for fabricating a semiconductor device with self-aligned contact  
A method for fabricating a semiconductor device includes forming electrode patterns over a substrate, wherein the electrode patterns include a hard mask, forming a passivation layer on the...
7895559 Method for designing structured ASICs in silicon processes with three unique masking steps  
A multi-function core base cell includes a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consisting of one or...
7888255 Method of forming an antifuse and a conductive interconnect, and methods of forming DRAM circuitry  
A first via opening is formed to a first conductor and a second via opening is formed to a second conductor. The first and second via openings are formed through insulative material. Then, the...
7888668 Phase change memory  
A phase change memory and the method for manufacturing the same are disclosed. The phase change memory includes a word line, a phase change element, a plurality of heating parts, and a plurality of...
7888705 Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same  
A method is disclosed for defining a dynamic array section to be manufactured on a semiconductor chip. The method includes defining a peripheral boundary of the dynamic array section. The method...
7883982 Monitor pattern of semiconductor device and method of manufacturing semiconductor device  
A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by...
Matches 1 - 50 out of 364 1 2 3 4 5 6 7 8 >