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8859357 Method for improving device performance using dual stress liner boundary  
An integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method...
8859343 3D semiconductor structure and manufacturing method thereof  
A semiconductor structure includes a plurality of stacked strips on a substrate and a plurality of conductive lines on the stacked strips. The stacked strips and the conductive lines are arranged...
8853815 Methods and apparatus for congestion-aware buffering using voltage isolation pathways for integrated circuit designs with multi-power domains  
A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with...
8844125 Method of making an electronic device having a liquid crystal polymer solder mask and related devices  
A method of making an electronic device includes forming a circuit layer on a liquid crystal polymer (LCP) substrate and having at least one solder pad. The method also includes forming an LCP...
8846458 Array substrate for in-plane switching mode liquid crystal display device and fabricating method thereof  
An array for an in-plane switching (IPS) mode liquid crystal display device includes a gate line formed on a substrate to extend in a first direction, a common line formed on the substrate to...
8835224 Distributing power with through-silicon-vias  
An integrated circuit with distributed power using through-silicon-vias (TSVs) is presented. The integrated circuit has conducting pads for providing power and ground located within the peripheral...
8834729 Method of making bondable printed wiring member  
A method for making a printed wiring member including wire-bondable contact pads and wear-resistant connector pads, the method includes the steps of a) providing a blank printed wiring member...
8817514 Non-volatile memory having 3D array of read/write elements with low current structures and methods thereof  
A three-dimensional array read/write (R/W) memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. It is preferable to operate...
8815652 Semiconductor device and method of manufacturing the same and semiconductor manufacturing device  
The present invention is a manufacturing method for a semiconductor device having steps of; aligning a program head 80 having a program dot array corresponding to each OTP-ROM cell array 21...
8815653 Packaging and connecting electrostatic transducer arrays  
Embodiments of a method for packaging cMUT arrays allow packaging multiple cMUT arrays on the same packaging substrate introduced over a side of the cMUT arrays. The packaging substrate is a...
8802509 Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection  
A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current...
8791447 Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells  
A nonvolatile memory cell includes first and second electrodes. Programmable material and a select device are received in series between and with the first and second electrodes. Current conductive...
8791507 Semiconductor device  
A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate...
8791513 Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same  
A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist...
8779434 Thin film transistor array and displaying apparatus  
A thin film transistor array is disclosed. The thin film transistor array includes plural gate electrodes formed on an insulation substrate, plural source electrodes formed above or under the gate...
8778742 Methods and systems for gate dimension control in multi-gate structures for semiconductor devices  
Methods and systems are disclosed for gate dimension control in multi-gate structures for integrated circuit devices. Processing steps for formation of one or more subsequent gate structures are...
8778710 Display substrate and method of fabricating the same  
A display substrate is provided that can prevent the opening of an upper conduction layer. The display substrate comprises a semiconductor layer pattern formed on a substrate, a data...
8772754 Semiconductor storage device comprising a memory cell array including a rectifying element and a variable resistor  
A method of manufacturing a semiconductor storage device according to an embodiment includes: stacking a first wiring layer; stacking a memory cell layer on the first wiring layer; and stacking a...
8772783 Display device  
The invention provides a technique to manufacture a display device with high image quality and reliability at low cost with high yield. According to the invention, a spacer is provided over a pixel...
8775112 System and method for increasing die yield  
The present invention systems and methods facilitate increased die yields by flexibly changing the operational characteristics of functional components in an integrated circuit die. The present...
8759163 Layout of a MOS array edge with density gradient smoothing  
A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by...
8759162 Nonvolatile semiconductor memory device and method of manufacturing the same  
A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive...
8754463 High density NOR flash array architecture  
In one embodiment of the invention, a memory includes wordline jogs and adjacent spacers. Spacers from different wordlines may contact one another on either side of a drain contact and consequently...
8742386 Oxide based memory with a controlled oxygen vacancy conduction path  
Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first...
8741696 Methods of forming pillars for memory cells using sequential sidewall patterning  
The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention...
8735861 Semiconductor storage device and method of manufacturing same  
A semiconductor storage device according to an embodiment includes a first conductive layer, a variable resistance layer, an electrode layer, a first liner layer, a stopper layer, and a second...
8735226 Methods and devices for forming nanostructure monolayers and devices including such monolayers  
Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in...
8735892 Semiconductor device using oxide semiconductor  
An object of one embodiment of the disclosed invention is to provide a semiconductor device having a novel structure in which stored data can be held even when power is not supplied and the number...
8735884 Semiconductor device including oxide semiconductor  
An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an...
8728875 Ballasted polycrystalline fuse  
A polycrystalline fuse includes a first layer of polycrystalline material on a substrate and a second layer of a silicide material on the first layer. The first and second layers are shaped to form...
8729702 Copper seed layer for an interconnect structure having a doping concentration level gradient  
A trench is opened in a dielectric layer. The trench is then lined with a barrier layer and a metal seed layer. The metal seed layer is non-uniformly doped and exhibits a vertical doping gradient...
8709880 Method for fabrication of a semiconductor device and structure  
A method of manufacturing semiconductor devices: providing a first device including a first die and second die, where the first die is diced from a first wafer, the second die is diced from a...
8710504 Flat display panel and method for forming the same  
The present invention proposes to a flat display panel and a method for forming the same. The flat display panel includes a plurality of rows of scan lines, a plurality of columns of data lines and...
8704353 Thermal management of stacked semiconductor chips with electrically non-functional interconnects  
A method of manufacturing is provided that includes fabricating a first plurality of electrically functional interconnects on a front side of a first semiconductor chip and fabricating a first...
8703562 Manufacturing method of random access memory  
A manufacturing method of a random access memory includes the following steps: providing a semiconductor structure having an array region and a peripheral region; forming a plurality of first...
8704204 Ferroelectric nanoshell devices  
Disclosed herein are nanoscale devices comprising one or more ferroelectric nanoshells characterized as having an extreme curvature in at least one spatial dimension. Also disclosed are...
8698519 Scalable non-blocking switching network for programmable logic  
A L-level permutable switching network (L-PSN) having switches and multiple levels of conductors that are used to connect a first plurality of conductors to other multiple sets of conductors within...
8698119 Nonvolatile memory device using a tunnel oxide as a current limiter element  
Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has improved device switching performance and...
8697498 Methods of manufacturing three dimensional semiconductor memory devices using sub-plates  
A method of manufacturing a Three Dimensional (3D) semiconductor memory device can be provided by forming at least one trench in a plate stack structure to divide the plate stack structure into a...
8691633 Metal structure for memory device  
A semiconductor device is provided that includes a substrate, a static random access memory (SRAM) unit cell formed in the substrate, a first metal layer formed over the substrate the first metal...
8685799 RRAM structure at STI with Si-based selector  
An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity...
8685798 Methods for forming through vias  
Methods for forming through vias in an integrated circuit package are disclosed. A substrate having a first surface is covered with an encapsulation layer of uncured material; the method includes...
8674333 Variable-resistance material memories and methods  
Variable-resistance memory material cells are contacted by vertical bottom spacer electrodes. Variable-resistance material memory spacer cells are contacted along the edge by electrodes. Processes...
8674356 Electrically measurable on-chip IC serial identifier and methods for producing the same  
An apparatus comprising an integrated circuit, an interconnect layer within said integrated circuit, and one or more connections. The integrated circuit may be configured to provide an electrically...
8673692 Charging controlled RRAM device, and methods of making same  
Disclosed herein is a novel charging controlled RRAM (Resistance Random Access Memory), and various methods of making such a charging controlled RRAM device. In one example, a device disclosed...
8674232 Device-embedded flexible printed circuit board and manufacturing method thereof  
A device-embedded flexible printed circuit board (FPCB) and a method of manufacturing the device-embedded FPCB are provided. The device-embedded FPCB includes: a first conductive layer; a first...
8673669 Method of making a CMOS image sensor and method of suppressing dark leakage and crosstalk for a CMOS image sensor  
A CMOS image sensor, in which an implantation process is performed on substrate under isolation structures each disposed between two adjacent photosensor cell structures. The implantation process...
8669155 Hybrid channel semiconductor device and method for forming the same  
A hybrid channel semiconductor device and a method for forming the same are provided. The method includes: providing a first semiconductor layer, the first semiconductor layer including an NMOS...
8669144 Methods of forming memory arrays  
Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed...
8664042 Method for fabrication of configurable systems  
A method to construct configurable systems, the method including: providing a first configurable system including a first die and a second die, where the connections between the first die and the...