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8936975 Touch panel, TFT-LCD array substrate and manufacturing method thereof  
A touch display comprising a first substrate formed with a common electrode; a second substrate formed with a gate line and a data line, wherein a first thin film transistor and a pixel electrode...
8934258 Motor controller  
A motor controller comprising multiple types of interfaces assigned automatically, including a mother circuit board and a daughter circuit board. The daughter circuit board is plugged into the...
8932912 One-time programmable device  
According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a...
8932911 Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects  
Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure...
8927346 Electrically and/or thermally actuated device  
An electrically, thermally, or electrically and thermally actuated device is disclosed herein. The device includes a substrate, a first electrode established on the substrate, an active region...
8927417 Semiconductor package signal routing using conductive vias  
A mechanism is provided by which signal travel distance within and between semiconductor device packages is reduced and substrate size and complexity can be reduced. This capacity is provided by...
8921898 Device including an array of memory cells and well contact areas, and method for the formation thereof  
A device includes an array of a plurality of memory cells, at least one N-well contact area and at least one P-well contact area. The memory cells are arranged in a plurality of rows and a...
8921165 Elimination of silicon residues from MEMS cavity floor  
The present invention generally relates to a MEMS device in which silicon residues from the adhesion promoter material are reduced or even eliminated from the cavity floor. The adhesion promoter is...
8921995 Integrated circuit package including a three-dimensional fan-out/fan-in signal routing  
An integrated circuit (IC) package is disclosed comprising a substrate including a plurality of substrate contacts; a semiconductor die including a plurality of die contacts; and a plurality of...
8912515 Manufacturing method for pipe-shaped electrode phase change memory  
A method for manufacturing a memory cell device includes forming a bottom electrode comprising a pipe-shaped member, a top, a bottom and sidewalls having thickness in a dimension orthogonal to the...
8906743 Semiconductor device with molded casing and package interconnect extending therethrough, and associated systems, devices, and methods  
Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the...
8907317 Silicon based nanoscale crossbar memory  
The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second...
8900900 Array substrate and manufacturing method thereof  
A manufacturing method of an array substrate includes the following steps. A substrate having pixel region and a peripheral region is provided. A plurality of pixel structures are formed in the...
8901530 Nonvolatile memory device using a tunnel oxide as a passive current steering element  
Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has improved device switching performance and...
8901738 Method of manufacturing an enhanced electromigration performance hetero-junction bipolar transistor  
Semiconductor devices with enhanced electromigration performance and methods of manufacture are disclosed. The method includes forming at least one metal line in electrical contact with a device....
8901526 Variable resistive memory device  
A variable resistive memory device capable of reducing contact resistance by including a contact layer having low contact resistance, the variable resistive memory device including a substrate...
8890233 3D memory array with improved SSL and BL contact layout  
A 3D memory device includes a plurality of ridges, in some embodiments ridge-shaped, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines...
8883569 Continuous mesh three dimensional non-volatile storage with vertical select devices  
A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are...
8883568 Method providing radial addressing of nanowires  
Disclosed is a method to construct a device that includes a plurality of nanowires (NWs) each having a core and at least one shell. The method includes providing a plurality of radially encoded NWs...
8878253 Semiconductor devices  
A semiconductor device and method of manufacturing a semiconductor device include a plurality of first active regions and a second active region being formed on a substrate. The second active...
8872324 Distributed semiconductor device methods, apparatus, and systems  
Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell...
8865288 Micro-needle arrays having non-planar tips and methods of manufacture thereof  
A micro-needle array having tips disposed along a non-planar surface is formed by shaping the wafer surface into a non-planar surface to define the tips of the micro-needles. A plurality of...
8859357 Method for improving device performance using dual stress liner boundary  
An integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method...
8859343 3D semiconductor structure and manufacturing method thereof  
A semiconductor structure includes a plurality of stacked strips on a substrate and a plurality of conductive lines on the stacked strips. The stacked strips and the conductive lines are arranged...
8853815 Methods and apparatus for congestion-aware buffering using voltage isolation pathways for integrated circuit designs with multi-power domains  
A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with...
8844125 Method of making an electronic device having a liquid crystal polymer solder mask and related devices  
A method of making an electronic device includes forming a circuit layer on a liquid crystal polymer (LCP) substrate and having at least one solder pad. The method also includes forming an LCP...
8846458 Array substrate for in-plane switching mode liquid crystal display device and fabricating method thereof  
An array for an in-plane switching (IPS) mode liquid crystal display device includes a gate line formed on a substrate to extend in a first direction, a common line formed on the substrate to...
8835224 Distributing power with through-silicon-vias  
An integrated circuit with distributed power using through-silicon-vias (TSVs) is presented. The integrated circuit has conducting pads for providing power and ground located within the peripheral...
8834729 Method of making bondable printed wiring member  
A method for making a printed wiring member including wire-bondable contact pads and wear-resistant connector pads, the method includes the steps of a) providing a blank printed wiring member...
8817514 Non-volatile memory having 3D array of read/write elements with low current structures and methods thereof  
A three-dimensional array read/write (R/W) memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. It is preferable to operate...
8815652 Semiconductor device and method of manufacturing the same and semiconductor manufacturing device  
The present invention is a manufacturing method for a semiconductor device having steps of; aligning a program head 80 having a program dot array corresponding to each OTP-ROM cell array 21...
8815653 Packaging and connecting electrostatic transducer arrays  
Embodiments of a method for packaging cMUT arrays allow packaging multiple cMUT arrays on the same packaging substrate introduced over a side of the cMUT arrays. The packaging substrate is a...
8802509 Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection  
A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current...
8791447 Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells  
A nonvolatile memory cell includes first and second electrodes. Programmable material and a select device are received in series between and with the first and second electrodes. Current conductive...
8791507 Semiconductor device  
A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate...
8791513 Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same  
A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist...
8779434 Thin film transistor array and displaying apparatus  
A thin film transistor array is disclosed. The thin film transistor array includes plural gate electrodes formed on an insulation substrate, plural source electrodes formed above or under the gate...
8778742 Methods and systems for gate dimension control in multi-gate structures for semiconductor devices  
Methods and systems are disclosed for gate dimension control in multi-gate structures for integrated circuit devices. Processing steps for formation of one or more subsequent gate structures are...
8778710 Display substrate and method of fabricating the same  
A display substrate is provided that can prevent the opening of an upper conduction layer. The display substrate comprises a semiconductor layer pattern formed on a substrate, a data...
8772754 Semiconductor storage device comprising a memory cell array including a rectifying element and a variable resistor  
A method of manufacturing a semiconductor storage device according to an embodiment includes: stacking a first wiring layer; stacking a memory cell layer on the first wiring layer; and stacking a...
8772783 Display device  
The invention provides a technique to manufacture a display device with high image quality and reliability at low cost with high yield. According to the invention, a spacer is provided over a pixel...
8775112 System and method for increasing die yield  
The present invention systems and methods facilitate increased die yields by flexibly changing the operational characteristics of functional components in an integrated circuit die. The present...
8759163 Layout of a MOS array edge with density gradient smoothing  
A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by...
8759162 Nonvolatile semiconductor memory device and method of manufacturing the same  
A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive...
8754463 High density NOR flash array architecture  
In one embodiment of the invention, a memory includes wordline jogs and adjacent spacers. Spacers from different wordlines may contact one another on either side of a drain contact and consequently...
8742386 Oxide based memory with a controlled oxygen vacancy conduction path  
Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first...
8741696 Methods of forming pillars for memory cells using sequential sidewall patterning  
The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention...
8735861 Semiconductor storage device and method of manufacturing same  
A semiconductor storage device according to an embodiment includes a first conductive layer, a variable resistance layer, an electrode layer, a first liner layer, a stopper layer, and a second...
8735226 Methods and devices for forming nanostructure monolayers and devices including such monolayers  
Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in...
8735892 Semiconductor device using oxide semiconductor  
An object of one embodiment of the disclosed invention is to provide a semiconductor device having a novel structure in which stored data can be held even when power is not supplied and the number...