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7405414 Method and apparatus for patterning a workpiece  
The present invention relates to a method for creating a pattern on a workpiece sensitive to electromagnetic radiation. Electromagnetic radiation is emitted onto a computer controlled reticle...
7402801 Inspecting method of a defect inspection device  
An inspecting method comprises the following steps. A plurality of defect inspection devices is formed on a wafer. Each defect inspection device comprises an insulating layer and a conductive layer...
7395518 Back end of line clone test vehicle  
A test vehicle comprises at least one product layer having a east one product circuit pattern on the product layer, and one or more clone layers formed over the product layer ( 1902 ). The one or...
7393703 Method for reducing within chip device parameter variations  
A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of...
7391023 Lithography tool image quality evaluating and correcting  
Electron beam lithography tool image quality evaluating and correcting including a test pattern with a repeated test pattern cell, an evaluation method and correction program product are disclosed....
7390682 Method for testing metal-insulator-metal capacitor structures under high temperature at wafer level  
A test methodology is provided for testing metal-insulator-metal (MIM) capacitor structures under high temperatures at the wafer level. A resistor is formed on a region of dielectric isolation...
7378290 Isolation circuit  
An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is...
7378289 Method for forming photomask having test patterns in blading areas  
A photomask and a method for forming a photomask are disclosed in which die regions that define features for a process step of a semiconductor fabrication process are formed on a photomask and a...
7373216 Method and apparatus for verifying a site-dependent wafer  
The present invention includes a method of verifying a Site-Dependent (S-D) wafer that includes receiving a first set of S-D wafers by one or more S-D processing elements in one or more processing...
7372072 Semiconductor wafer with test structure  
The invention relates to a semiconductor wafer ( 1 ) having a plurality of first sawing regions ( 201 - 211 ) running parallel to one another in a first direction (X) and a plurality of second...
7368304 Fabricating die with separate test pads selectively coupled to cores  
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die....
7339388 Intra-clip power and test signal generation for use with test structures on wafers  
The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of...
7335518 Method for manufacturing semiconductor device  
In a manufacturing method for a semiconductor device, a main body wafer is formed, and a monitor wafer on which a monitor element is formed is provided. Characteristics of the main body wafer are...
7316935 Reticle for layout modification of wafer test structure areas  
Techniques are provided for forming die on wafers with large area test structures between primary die. A reticle is used to pattern each die. The pattern on the reticle forms a primary die and test...
7301225 Multi-row lead frame  
A lead frame ( 10 ) for a semiconductor device includes a first row of terminals ( 12 ) surrounding a die receiving area ( 14 ) and a second row of terminals ( 16 ) spaced from and surrounding the...
7282374 Method and apparatus for comparing device and non-device structures  
The present invention provides a method and apparatus for comparing device and non-device structures. The method includes determining at least one characteristic parameter associated with at least...
7276386 Semiconductor device and method of manufacturing the same  
A method of manufacturing a semiconductor device includes the steps of forming barrier metals on first electrodes provided on a chip of the semiconductor device, implementing a predetermined test...
7265445 Integrated circuit package  
An IC package includes a package body of non-conductive material. A conductive heat-sink pad includes an interior pad portion located within an interior of the package body. An exterior pad portion...
7256055 System and apparatus for using test structures inside of a chip during the fabrication of the chip  
The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of...
7220990 Technique for evaluating a fabrication of a die and wafer  
The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of...
7217579 Voltage contrast test structure  
A method for electrically testing a semiconductor wafer during integrated-circuit fabrication process, the method including: (i) providing a scanning charged-particle microscope (SCPM), having a...
7211453 Method and apparatus for personalization of semiconductor  
A system for making small modifications to the pattern in standard processed semiconductor devices. The modifications are made to create a small variable part of the pattern against a large...
7197726 Test structures for estimating dishing and erosion effects in copper damascene technology  
A test structure combines a first structure ( 1010 ) for erosion evaluation with a second structure ( 1000 ) for extraction of defect size distributions. The first structure ( 1010 ) is a loop...
7192790 Manufacturing method for a semiconductor device  
A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic...
7192505 Wafer probe for measuring plasma and surface characteristics in plasma processing environments  
There is provided by this invention a wafer probe for measuring plasma and surface characteristics in plasma processing environment that utilizes integrated sensors on a wafer substrate. A...
7186576 Stacked die module and techniques for forming a stacked die module  
Embodiments of the present technique relate to forming die stacks. Specifically, embodiments of the present technique include a method of forming and testing semiconductor die comprising forming a...
7179661 Chemical mechanical polishing test structures and methods for inspecting the same  
Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings...
7176486 Structure of test element group wiring and semiconductor substrate  
A structure of test element group wiring includes, in addition to an electrode on a substrate including one or more layers of insulating films, and real wirings electrically connected to the...
7166480 Particle control device and particle control method for vacuum processing apparatus  
A particle control device and a particle control method are capable of controlling the occurrences of particles in a vacuum reactor. The particle control device is used in a vacuum processing...
7163829 Method of integration testing for packaged electronic components  
A method of integration testing for packaged electronic components is capable of improving a conventional testing for packaged electronic components. In this method, non-tested sides of the...
7154116 Rewiring substrate strip with a number of semiconductor component positions  
A rewiring substrate strip with a number of semiconductor component positions and semiconductor components, which are arranged in rows and columns on the rewiring substrate strip also includes are...
7138653 Structures for stabilizing semiconductor devices relative to test substrates and methods for fabricating the stabilizers  
Stabilizers to be disposed on a surface of a semiconductor device or test substrate and methods of fabricating and disposing the stabilizers on semiconductor devices and test substrates....
7135412 Method to control a management system to control semiconductor manufacturing equipment  
In the control method in a management system of semiconductor manufacturing equipment to enhance a product yield through a control of etching process, information of a corresponding lot for the...
7095045 Semiconductor device and manufacturing method thereof  
A semiconductor device includes a substrate, a pad electrode formed on the substrate and a bump electrode formed on the pad electrode, wherein the pad electrode has an irregular flaw, and there is...
7077120 Substrate cutting method  
A method of producing a semiconductor device constructed by arranging a plurality of substrates, on each of which, thin film semiconductor elements two-dimensionally arranged are installed. The...
7076178 Fiber optic transceiver array and fiber optic transceiver channel for short wave fiber optic communications  
A fiber optic transceiver array and a fiber optic transceiver channel are provided for short wave fiber optic communications. A fiber optic transceiver array for short wave fiber optic...
7074629 Test patterns for measurement of effective vacancy diffusion area  
A test pattern ( 100, 200, 300, 400, 600, 700 ) has a first metal structure ( 102 ) disposed on a substrate ( 352 ), one or more intermediate layers ( 358 ) disposed above the first metal structure...
7060511 Evaluation method of a field effect transistor  
The present invention provides a method for estimating resistance value of an LDD region that works in an actual FET and forming an optimum LDD region. Therefore, the present invention provides an...
7056751 Method and system for increasing yield of vertically integrated devices  
A method for increasing the manufacturing yield for a vertically integrated device is disclosed. The devices are composed of one or more multiple layer die. The number of functioning layers of each...
7049700 Semiconductor test board having laser patterned conductors  
A method for fabricating semiconductor components is performed using a laser scanner and a laser imaging process. A substrate, such as a semiconductor wafer, containing multiple semiconductor...
7037733 Method for measuring temperature, annealing method and method for fabricating semiconductor device  
When the emissivity ε on the reverse face of a substrate 10 is measured during annealing processing for the substrate 10, films made from a material that varies the emissivity ε, such as a...
7033843 Semiconductor manufacturing method and semiconductor manufacturing apparatus  
A semiconductor manufacturing method whereby reactive gas processing such as selective epitaxial growth can be carried out with high precision by correctly adjusting conditions during processing is...
7029934 Method and apparatus for testing TFT array  
A testing method for a TFT array substrate using a self-emitting element drive where pixels are arranged in a matrix and each pixel comprises a drive transistor having a gate formed from a first...
7026171 Rapid thermal annealing process  
A rapid thermal annealing (“RTA”) process providing for an RTA equipment is disclosed. The RTA equipment has a pyrometer providing for measuring an operation parameter, e.g., a temperature of...
7000822 Wire bond integrity test system  
An improved bond integrity test system is provided by eliminating the spring loaded wire spool cover which contributes to particulate matter, and by addition of a second contact diverter in the...
6995027 Integrated semiconductor structure for reliability tests of dielectrics  
A test structure for assessing the reliability of a dielectric of a circuit element in an integrated circuit includes a plurality of test circuit elements and a plurality of contact pads, wherein...
6991943 Process for preparation of semiconductor wafer surface  
A method for adjusting the resistivity in the surface of a semiconductive substrate including selective measurement and counter-doping of areas on a major surface of a semiconductive substrate.
6985674 Fiber optic transceiver array and fiber optic transceiver channel for short wave fiber optic communications  
A fiber optic transceiver array and a fiber optic transceiver channel are provided for short wave fiber optic communications. A fiber optic transceiver array for short wave fiber optic...
6984531 Electrical field alignment vernier  
A test structure pattern includes a first comb having a first set of tines, and a second comb having a second set of tines of the same width and spacing as the first set of tines. When the test...
6977128 Multi-layered semiconductor structure  
A multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly...
Matches 1 - 50 out of 163 1 2 3 4 >