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8175213 System and method for setting counter threshold value  
A system and method for configuring threshold values for fixed time delay counters of a System on a Chip (SoC) uses a reference clock signal and one or more frequency sub-range control signals...
8064567 Method and device for the incremention of counter statuses stored in memory cells of a memory  
A method for the incrementation of counter statuses in memory cells, which are arranged respectively in rows and columns of a first memory adds a “1” to the memory content of a memory cell of a sec...
8027425 Asynchronous loadable down counter  
The disclosed embodiments relate to an asynchronous down counter, which can be loaded with any value N and then decrement exactly N times. The counter comprises an array of cells, wherein each cell...
7877759 System for efficient performance monitoring of a large number of simultaneous events  
A system for monitoring a large number of simultaneous events implements a hybrid counter array device having a first counter portion comprising counter devices, each counter device for receiving...
7861126 Implementation-efficient multiple-counter value hardware performance counter  
An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array...
7809901 Combined parallel/serial status register read  
Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined parallel and serial read scheme. One...
7782995 Low latency counter event indication  
A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences...
7735031 Method and apparatus for self identification of circuitry  
A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic...
7688931 Space and power efficient hybrid counters array  
A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing...
7573969 Counter using shift for enhanced endurance  
A counting device includes a set of memory cells, which are configured to store respective bits of a count code. A controller is coupled to the memory cells so as to increment, in response to...
7551706 Counter device and counting method  
A counter device includes: a rewritable counter having a non-volatile memory which requires sector erasure to once turn all data in a sector into high data, prior to changing low data into high...
7526059 Balanced Grey code utilization to increase NVM endurance  
A counting device includes a set of memory cells, including multiple groups of the memory cells configured to store count words of a count code, which include a less significant word and a more...
7461383 Method and apparatus for efficient performance monitoring of a large number of simultaneous events  
A system for monitoring a large number of simultaneous events implements a hybrid counter array device having a first counter portion comprising counter devices, each counter device for receiving...
7437622 Implementation-efficient multiple-counter value hardware performance counter  
An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array...
7426253 Low latency counter event indication  
A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences...
7154983 Method of operating a first-in first-out (FIFO) circuit  
The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled...
7085341 Counter with non-uniform digit base  
A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment...
7065607 System and method for implementing a counter  
A counter is provided which can be implemented in flash memory allowing longer life through fewer erasures. The counter is incremented using a method that minimizes bit transitions from 1 to 0. In...
6944256 Optimizing use of statistics counters  
Optimizing statistics counter use is disclosed. A total number of counter bits to be used to track two or more statistics is determined. The total number of counter bits is allocated among the two...
6922619 System and method for selectively limiting tractive effort to facilitate train control  
Method for controlling the level of tractive efforts in a train having a first locomotive at a head end of the train, constituting a lead locomotive, and a second locomotive positioned in the train...
6922456 Counter system and method  
A system and method for performing counting operations for a plurality of components is disclosed. A memory stores a plurality of counts from different components. The memory is coupled to a...
6895070 Counter circuit  
The counter circuit comprises the initial value single port RAM having N initial value registers allocated for memorizing N initial values, the counter register single port RAM having N counter...
6882697 Digital counter  
A digital counter with a dial position having a hardware part which determines the n lowest-value bits of the dial position and a software part which determines the remaining higher-value bits of...
6839397 Circuit configuration for generating control signals for testing high-frequency synchronous digital circuits  
A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage shift register which is clocked at a...
6792065 Method for counting beyond endurance limitations of non-volatile memories  
A digital counter that uses non-volatile memories as storage cells, wherein the storage cells are sub-divided into two groups, one for the implementation of a rotary counter that keeps track of the...
6556645 Multi-bit counter  
A multi-bit counter of the present invention is capable of high-speed operation because the time needed for increasing count values and combining count bits for a carry can be minimized by...
6542568 Soap dispenser having reward program  
A system for rewarding and encouraging compliance with a predetermined personal hygiene standard in a hygiene compliance program. The system comprises a fluid dispenser. The fluid dispenser...
6519311 Overflow detector for FIFO  
The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled...
6501817 Area efficient redundancy multiplexer circuit technique for integrated circuit devices providing significantly reduced parasitic capacitance  
An improved integrated circuit area efficient redundancy multiplexer circuit technique provides similar functionality to conventional CMOS transmission, or “pass” gates while concomitantly red...
6473484 Binary counter and method for counting to extend lifetime of storage cells  
A digital counter and method for counting are implemented which minimize fatigue-related failure in the storage element for the count value. The counting sequence is chosen such that the...
6459751 Multi-shifting shift register  
A multi-shifting shift register is adapted for outputting a selected address signal to a memory unit, and includes a control circuit for outputting a number (i) of shift signals and a timing pulse...
6421408 Counter logic for multiple memory configuration  
The present invention is an efficient system and method for flexible masking of output bits from a counter. The maskable counter system and method of the present invention modify the chain carry...
6385275 Assembly for generating a consecutive count  
An assembly for generating a consecutive count includes an n-stage binary counter (24) incrementable by counting pulses in successive cycles and an EEPROM (10) in which an item of information...
6366634 Accelerated carry generation  
An address binary counter for an interleaved having an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells includes as many stages as the bits...
6337893 Non-power-of-two grey-code counter system having binary incrementer with counts distributed with bilateral symmetry  
A gray-code counter system (AP1) for a RAM-based FIFO comprises a read pointer (10), a write pointer (20), and a detector (30). The read pointer includes a gray-code decoder (11), a binary...
6324238 Bit counter stage, particularly for memories  
A bit counter stage, particularly for memory addresses, including: a master storage circuit; a slave storage circuit which is connected to the master storage circuit; a circuit for enabling the...
6320927 Electronic counter  
It is an object of the present invention to make it possible to optionally configure various types of electronic counters. Therefore, the present invention is provided with a one-chip microcomputer...
6314154 Non-power-of-two Gray-code counter and binary incrementer therefor  
Non-power-of-two Gray-code counters, including modulos 10, 12, 14, and 22 are disclosed, along with a sequencing method they employ. Each counter includes a register for storing an N-bit, e.g.,...
6314155 Counting circuit with rewritable non-volatile memory, and counting method  
A frequency counter 1 includes a binary counter section 11 having a binary counter 20 for counting up frequency data, and a EEPROM counter section 12 having an EEPROM 40 containing frequency data....
6301322 Balanced dual-edge triggered data bit shifting circuit and method  
A balanced dual-edge triggered bit shifting circuit includes a clock circuit to generate low skew, or edge-aligned, complementary clock signals, and a shift register that shifts a data bit in...
6269138 Low power counters  
A low power counter for cycling through a predetermined sequence of states in response to pulses on an input line includes a number of counter blocks, corresponding to the number of bits of the...
6249562 Method and system for implementing a digit counter optimized for flash memory  
A system and method of implementing a digit counter having a plurality of digits, ranging from a least significant digit (LSD) to a maximum positional digit (MDP), is described. In one embodiment,...
6232808 Irregular interval timing  
A single large register increments ticks of a high-speed clock. A single compare register is associated with the clock register, the compare register preferably being of equivalent length to the...
6215837 Pipe counter signal generator processing double data in semiconductor device  
Disclosed is a DDR SDRAM device which may be implemented by simply modifying a pipe counter for an SDR SDRAM device. A pipe counter comprising according to the present invention comprises: a...
6208705 Electronic counter for a non-volatile memory device integrated on a semiconductor  
An electronic counter for a semconductor-integrated non-volatile memory device includes a single count cell connected with its output to at least one storage element The count cell comprises a...
6097781 Shared counter  
A shared counter performs multiple counting functions in an electronic circuit, such as a memory integrated circuit. An input selection circuit selects one of M input data sets at a given time to...
6088422 One-pin shift register interface  
A register using a single pin to provide two or more control signals (e.g., clock and data signals). The present invention decodes a three state input waveform to generate a clock/write signal and...
6078636 Counter circuit and semiconductor memory having counter circuit as address counter circuit  
A counter circuit, which may be on a semiconductor integrated circuit, that is applicable to both a linear sequence and an interleave sequence and is capable of setting a burst length at 1, 2, 4,...
6075833 Method and apparatus for counting signal transitions  
A circuit for counting events occurring between two different clock domains includes a gray code counter having at least two stages. The gray code counter is incremented by the event to be counted....
6061417 Programmable shift register  
A programmable shift register in which the length (e.g., number of bits), number and location of taps, operating mode (i.e., counting up/down) and number of skip states are configured by...
Matches 1 - 50 out of 253 1 2 3 4 5 6 >