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7620857 |
Controllable delay device
Two delay chains having in each case n series-connected unidirectional delay elements are provided for controllably delaying electrical signals between a circuit input and at least one circuit...
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7620137 |
System and method for clock drift correction for broadcast audio/video streaming
A clock rate used in rendering broadcast streaming audio/video data is adjusted to converge on a clock rate associated with broadcasting the streaming data. The clock rate is adjusted by monitoring...
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7616726 |
Optical disk apparatus and PLL circuit
With the objective of providing a stable PLL circuit and improving readout performance of an optical disk apparatus equipped with PRML, using the PLL circuit, phase detectors are respectively...
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7616708 |
Clock recovery circuit
A clock recovery circuit comprising an initial delay select circuit, a delay locked loop and a clock synthesizer circuit is provided. The initial delay select circuit comprises an initial timing...
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7613268 |
Method and apparatus for designing a PLL
A method and apparatus for designing a PLL enables initial component characteristics and design specifications of the PLL to be specified. Time constants for a loop filter that would be required to...
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7613267 |
Digitally-synthesized loop filter method and circuit particularly useful for a phase locked loop
In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as...
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7613265 |
Systems, methods and computer program products for high speed data transfer using an external clock signal
Systems, methods and computer program products for capturing data. The methods include receiving an external clock signal having a first frequency, a first edge and a second edge. A clock period of...
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7613254 |
Phase detector for comparing phases of data and a plurality of clocks
A phase detector that compares the phases of data and four-phase first to fourth clocks having a half rate of the data and being 90° out of phase with one another. Exemplary embodiments of the...
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7612625 |
Bang-bang architecture
In one embodiment, the present invention includes an apparatus having a voltage controlled oscillator (VCO) to generate a first clock signal having a frequency controlled by a bias current coupling...
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7612617 |
Voltage-controlled oscillator gain calibration for two-point modulation in a phase-locked loop
A phase-locked loop (PLL) is arranged to receive high-pass data at a first input and low-pass data at a second input. A first digital input is coupled to a primary path through a digital-to-analog...
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7612589 |
Phase-locked loop and control method utilizing the same
A phase-locked loop includes a processing unit, a voltage-controlled oscillator, and a control unit. The processing unit generates a control voltage to a node according to a phase difference...
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7610030 |
Wireless transmit-only apparatus and method
A wireless transmit-only apparatus ( 20 ) has a controller ( 21 ) that responds to a user interface 25 by correlating specific user input with a corresponding characterizing transmission...
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7609799 |
Circuit, system, and method for multiplexing signals with reduced jitter
A multiplexer circuit, system and method is provided herein for multiplexing signals with reduced jitter by eliminating all crosstalk and power supply noise injection within the multiplexer...
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7609797 |
Circuit, system, and method for preventing a communication system absent a dedicated clocking master from producing a clocking frequency outside an acceptable range
A communication system, clock recovery circuit, and method are provided for allowing data to be transmitted across a communication system and between clock recovery circuits absent a clock master...
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7609792 |
Multiple-input multiple-output multichip transceiver with correlated clock signals
A multichip transceiver operates as part of a multiple-input multiple-output communication system. First receiver circuitry on a first integrated circuit processes radio-frequency (RF) signals...
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7606343 |
Phase-locked-loop with reduced clock jitter
The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a...
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RE40939 |
Multi-phase locked loop for data recovery
The present invention provides a multi-phase-locked loop without dead zone, which can reduce clock jitter and provide larger tolerance for data random jitter. It generates and output multiple sets...
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7603095 |
Apparatus and method of switching intervals
The present invention provides a way of hysteretic switching for efficiently reducing the heavy switching between two adjacent coarse intervals. The present invention disposes a number of fine...
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7602253 |
Adaptive bandwidth phase locked loop with feedforward divider
In some embodiments, a chip includes first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals...
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7599462 |
Hybrid analog/digital phase-lock loop with high-level event synchronization
A hybrid analog/digital phase-lock loop with high-level event synchronization provides a mechanism for generating a low-jitter clock from a timing reference that has a high jitter level and...
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7599460 |
Transmitting apparatus
A device including a line interface for additionally installing a line is installed in a terminal repeater device which takes a work and protection redundancy configuration based on a criterion...
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7599005 |
Method for synchronizing video signals
A method for synchronizing video signals is provided wherein a synchronization state signal is generated which is descriptive for the synchronization of an output of fields/frames with the...
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7596173 |
Test apparatus, clock generator and electronic device
There is provided a clock generator for generating a single-phase clock into which jitter has been injected, having a multi-phase clock generating section for generating a plurality of clock...
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7593500 |
Apparatus for coordinating triggering of analog-to-digital conversions relative to pulse width modulation cycle timing
A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM,...
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7593498 |
Method and apparatus for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications
Methods and apparatus are provided for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications. An interface is provided for use...
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7590387 |
High accuracy voltage controlled oscillator (VCO) center frequency calibration circuit
Methods and systems for calibrating a frequency of a circuit are disclosed herein and may comprise dividing a feedback frequency of an output frequency signal to generate a divided frequency...
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7590212 |
System and method for adjusting the phase of a frequency-locked clock
A clock signal regeneration system and method to adjust the phase of a frequency-locked clock signal is provided. The system includes a numerically controlled oscillator, a clock source, and an...
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7590211 |
Programmable logic device integrated circuit with communications channels having sharing phase-locked-loop circuitry
Integrated circuits such as programmable logic device integrated circuits are provided that have resource-efficient receiver circuitry. In source-synchronous system environments, an integrated...
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7590163 |
Spread spectrum clock generation
There is provided a method of modifying a first clock to generate a second clock with reduced electromagnetic interference (EMI). The method comprises receiving the first clock, generating an...
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7587017 |
Carrier phase synchronization system for improved amplitude modulation and television broadcast reception
Systems and methods are described for carrier phase synchronization for improved AM and TV broadcast reception. A method includes synchronizing the phase of a carrier frequency of a broadcast...
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7587015 |
Asynchronous digital data capture
The present invention provides asynchronous digital capture by first, capturing the digital output of the device under test (DUT) clock on an automated test equipment (ATE) digital channel. Next,...
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7583774 |
Clock synchroniser
A clock synchronizer, for generating a local clock signal synchronized to a received clock signal, is described and claimed, along with a corresponding clock synchronization method. The clock...
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7583773 |
Frequency synthesizing device with automatic calibration
A frequency synthesizer with automatic calibration includes a voltage-controlled oscillator, which has several working bands for receiving a coarse-tuned signal and a fine-tuned signal and...
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7580629 |
Los beat detector
A loss of signal beat detector makes use of multiplication of a local clock signal and a recovered clock signal to obtain frequency deltas used to indicate loss signal. Through a hardware...
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7580498 |
Closed loop control system and method of dynamically changing the loop bandwidth
The invention provides a method for dynamically changing the loop bandwidth of a closed loop control system. At least one loop bandwidth parameter controls the loop bandwidth of the closed loop...
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7580497 |
Clock data recovery loop with separate proportional path
A clock data recovery loop that can be used over a wide range of data rates and maintain second-order behavior includes a nonlinear (e.g., Bang-Bang) phase detector, a charge pump, an RC loop...
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7580496 |
Device for receiving series data
A circuit for receiving digital data arriving in series comprising a circuit for generating a reference dock and a circuit for oversampling the received data memorizing the samples sampled at the...
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7580491 |
Quarter-rate clock recovery circuit and clock recovering method using the same
A quarter-rate clock recovery circuit includes a clock generator, a phase interpolation unit, a phase detector, and a controller. The clock generator generates first through fourth clocks having a...
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7580483 |
Trimming of local oscillation in an integrated circuit radio
A method and apparatus for trimming of a local oscillation within a radio frequency integrated circuit (RFIC) includes processing that begins when an RFIC receives a radio frequency (RF) signal...
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7580443 |
Clock generating method and clock generating circuit
In a clock generating circuit, while a PLL (Phase-Locked Loop) circuit and a modulator are employed, when a frequency dividing ratio of a feedback-purpose frequency divider in the PLL circuit is...
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7579953 |
Detecting a self-jammer signal in an RFID system
A radio frequency device capable of differentiating self-jammer signals.
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7577226 |
Clock recovery circuitry
Clock recovery circuitry for recovering a clock signal from a data signal is disclosed. The clock recovery circuitry comprises sampling unit ( 46 ) for sampling the data signal at a plurality of...
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7577225 |
Digital phase-looked loop
Embodiments of the invention include an integrated circuit including a phase-locked loop (PLL). The integrated circuit includes a phase detector, a frequency detector, a loop filter, a...
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7577224 |
Reducing phase offsets in a phase detector
In one embodiment, the present invention includes a system having an amplifier to receive an incoming signal and a recovery circuit coupled to the amplifier that includes a phase detector to adjust...
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7577215 |
Angle demodulation apparatus, local oscillation apparatus, angle demodulation method, local oscillation signal generating method, recording medium and computer data signal
An FM modulation signal is mixed with a pair of first local oscillation signals to be converted to a pair of base band signals. The base band signals are respectively mixed a pair of second local...
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7576621 |
Film bulk acoustic resonator calibration
Film bulk acoustic resonators (FBARS) have resonant frequencies that vary with manufacturing variations, but tend to be matched when in proximity on an integrated circuit die. FBAR resonant...
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7576578 |
Frequency synthesizer and charge pump circuit used for the same
A frequency synthesizer includes an AND circuit ( 17 ) for detecting whether a frequency synthesizer is in a lock state according to a signal outputted from an Up terminal and a Down terminal of a...
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7573967 |
Input threshold adjustment in a synchronous data sampling circuit
A data sampler system receives a high-speed data stream and uses a first set of data samplers for sampling the data stream at a first set of clock phase angles to produce a first set of sequential...
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7573955 |
Digital phase locked loop for sub-μ technologies
A digital phase locked loop has a digitally controlled oscillator for generating an output frequency, a phase detector device for detecting the phase difference between a reference frequency and an...
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7573348 |
Arrangement and method for determining a gradient factor for a digitally controlled oscillator, and phase locked loop
An arrangement for determining a gradient factor for a digitally controlled oscillator has a data alignment device and an identification device. The data alignment device can be supplied a...
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