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9036762 Generating compatible clocking signals  
Techniques are disclosed relating to generating compatible clock signals. In one embodiment, an apparatus is configured to receive an input clock signal and a reference clock signal. In this...
9031181 Method and apparatus for controlling clocking of transceivers in a multi-port networking device  
A multi-port information communication system includes a reference clock signal generator configured to generate a reference clock signal. The system also includes a phase controller configured to...
9025965 Digital phase locked loop having insensitive jitter characteristic for operating circumstances  
Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital...
9025650 Multiple receivers in an OFDM/OFDMA communication system  
A signal receiver is configured to receive multiple time-domain input signals. A plurality of the input signals among the multiple time-domain input signals is selected and transformed into...
9020088 Digital system and method of estimating quasi-harmonic signal non-energy parameters using a digital Phase Locked Loop  
The present invention proposes a digital system and method of measuring (estimating) non-energy parameters of the signal (phase, frequency and frequency rate) received in additive mixture with...
9008196 Updating interface settings for an interface  
A computer system includes a processor, and the processor includes at least one interface for communicating with an electronic component. Each of the at least one interface has a set of interface...
9001275 Method and system for improving audio fidelity in an HDMI system  
HDMI is a digital audio and video communications protocol commonly used in consumer electronics. HDMI is particularly synonymous with high fidelity audio and video. Even though HDMI is a digital...
9001869 Compact low-power fully digital CMOS clock generation apparatus for high-speed SerDes  
A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with...
8995598 Low jitter clock recovery circuit  
A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase...
8994425 Techniques for aligning and reducing skew in serial data signals  
A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first...
8989329 Eye width measurement and margining in communication systems  
Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver...
8982974 OFDM clock recovery  
Receiver synchronization techniques (RST), contributing more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of...
8964925 Multi-rate control loop for a digital phase locked loop  
Methods and systems to generate control signals for timing recovery of a signal received over baseband communications systems are disclosed. The timing control circuit uses a multi-rate DSP...
8964899 Receiving circuit  
Disclosed is a receiving circuit which includes: a data selection circuit selecting two input data located while placing in between the center phase of one unit interval of a binary input data; a...
8964919 System and method for determining a time for safely sampling a signal of a clock domain  
A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a phase estimate of a first clock domain is calculated based on a...
8964922 Adaptive frequency synthesis for a serial data interface  
Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally....
8948333 Clock frequency error detecting device  
A clock frequency error detecting device includes a system storage portion which stores a synchronization system based on at least one of several types of frame synchronization signals included in...
8947167 Reference-less frequency detector  
Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the...
8942317 Carrier offset correction of a received signal  
Apparatuses, methods and systems for mitigating carrier offset of a received signal are disclosed. One embodiment of a receiver includes a receiver chain operative to receive a communication...
8942333 Apparatus and methods for clock alignment for high speed interfaces  
Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY interface in a system on a chip...
8929500 Clock data recovery with out-of-lock detection  
The disclosed clock-data recovery architecture includes out-of-lock (including false lock) detection. Out-of-lock detection is accomplished by sampling retimed/recovered data with positive and...
8923467 Clock and data recovery using receiver clock spread spectrum modulation and offset compensation  
A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the rate of change of an offset between...
8923468 Clock and data recovery circuit selectively configured to operate in one of a plurality of stages and related method thereof  
An exemplary clock and data recovery circuit includes a serial data input node arranged for receiving a serial data; a reference clock input node arranged for receiving a reference clock; a...
8917806 Digital phase-locked loop and phase/frequency detector module thereof  
A phase/frequency detector module, applicable to a digital phase-locked loop, includes: an edge detector for receiving a reference clock signal and a counting clock signal, where when a positive...
8901974 Phase locked loop and method for operating the same  
The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit...
8903031 Low jitter clock recovery circuit  
A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase...
8897412 Method and apparatus for phase noise mitigation  
An approach is provided to mitigate phase noise by correcting common phase error and inter-carrier-interference in a received signal. The approach involves determining a received signal includes...
8891667 Transmission apparatus, transmission method and method of altering transmission band  
A transmission apparatus for transmitting frames accommodating client data over a transmission network, comprising a clock generation unit that generates a clock for timing processing period of...
8885773 Radio architecture for an ultra low power receiver  
An ultra low power radio receiver architecture based on phase locked loop is provided. Embodiments of an ultra low power radio receiver architecture based on phase locked loop can detect a complex...
8885775 Dynamic optimization of carrier recovery performance for communication systems  
Apparatuses, systems, and methods are directed to maintaining optimal carrier tracking performance in view of operating conditions that prevail. Such configurations employ a phase lock loop that...
8884671 Phase-locked loop system and operation  
A phase-locked loop system has a controlled oscillator that provides an output clock signal based on a oscillator control signal, a feedback path configured to provide a feedback signal based on...
8884672 Configurable digital-analog phase locked loop  
A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter,...
8879681 System and method for determining a time for safely sampling a signal of a clock domain  
A system and method are provided for determining a time for safely sampling a signal of a dock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a...
8873693 Phase averaging-based clock and data recovery  
In one embodiment, a method includes adjusting a first frequency of a first clock signal based on a frequency difference between the first frequency and a reference clock signal frequency of a...
8864376 Temperature sensing circuit  
A temperature sensing circuit includes a signal generation unit including a delay line and generating a source signal with a pulse width corresponding to a delay value of the delay line, a pulse...
8867597 Method, device and system for clock dejitter  
The present invention discloses a clock dejitter method comprising: a data sending adapter module inputting data with a system clock and using a sending clock to send data; a clock dejitter module...
8861580 Method and apparatus for determining one or more channel compensation parameters based on data eye monitoring  
Methods and apparatus are provided for determining one or more channel compensation parameters based on data eye monitoring. According to one aspect of the invention, a method is provided for...
8855258 Transmitters and receivers using a jitter-attenuated clock derived from a gapped clock reference  
A system and method are provided for resynchronizing a transmission signal using a jitter-attenuated clock derived from an asynchronous gapped clock. A first-in first-out (FIFO) memory accepts an...
8848850 Pulse width modulation receiver circuitry  
Mechanisms and techniques to evaluate data for a high speed I/O receiver logic. In an embodiment, a receiver circuit shifts a bit into a shift circuit in response to a rising edge of a data...
8848852 Antenna grouping and group-based enhancements for MIMO systems  
Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter has at least three transmit...
8836391 Plesiochronous clock generation for parallel wireline transceivers  
A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder, at least one digital frequency mismatch number; decoding, with the...
8829958 Clock and data recovery circuitry with auto-speed negotiation and other possible features  
An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock...
8824612 Apparatuses, circuits, and methods for reducing metastability in data synchronization  
Apparatuses, circuits, and methods are disclosed for reducing or eliminating unintended operation resulting from metastability in data synchronization. In one such example apparatus, a sampling...
8816776 Loss of lock detector for clock and data recovery system  
An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The...
8811557 Frequency acquisition utilizing a training pattern with fixed edge density  
A method for frequency acquisition comprising steps of, acquiring samples of an input signal, each sample having edges, making sets with a fixed number of consecutively taken samples, numbering...
8810291 Phase-locked loop  
The PLL includes a voltage-controlled oscillator (VCO), a frequency down conversion circuit, a phase-frequency detector (PFD), and an adjusting circuit. The VCO is configured to generate an output...
8804892 Frequency and phase acquisition of a clock and data recovery circuit without an external reference clock  
A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without...
8804888 Wide band clock data recovery  
The present disclosure provides a clock data recovery circuit that includes a phase locked loop unit, a delay locked loop unit and digital clock data recovery unit. The phase locked loop unit...
8804877 Apparatus and method for correcting phase error  
An apparatus for correcting a phase error is provided. The apparatus includes an error estimating module and a correcting module. The error estimating module receives a phase-shift keying signal,...
8804891 Frequency detector and method for detecting frequencies  
A frequency detector includes a multi-phase clock generation unit, a sampling unit connected to the multi-phase clock generation unit and a digital logic unit connected to the sampling unit. An...