Matches 51 - 100 out of 237 < 1 2 3 4 5 >
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7003066 Digital phase locked loop with phase selector having minimized number of phase interpolators  
In one embodiment of the invention, a phase selection unit for generating a recovered clock signal (SCLK), a phase select signal generator generates a phase select signals in response to a FWD...
7003065 PLL cycle slip detection  
A cycle slip detector interfaces with a phase/frequency detector (PFD), such as might be used in a phase-locked loop circuit (PLL), and indicates when cycle slips occur in the PFD. Typically, the...
6993108 Digital phase locked loop with programmable digital filter  
In a digital filter of a DPLL (digital phase locked loop) for minimizing the bit error rate for multiple communications protocols, a first reloadable register portion stores a TBW (total bandwidth)...
6977959 Clock and data recovery phase-locked loop  
A clock recovery circuit that operates at a clock speed equal to one-half the input data rate is presented. The clock recovery circuit uses dual input latches to sample the incoming serial data on...
6973152 Exploiting shortest path for improved network clock distribution  
Apparatus and methods are provided for exploiting the existence of a shortest path between a source device and a destination device by identifying the shortest path and using the signal which has...
6973147 Techniques to adjust a signal sampling point  
Techniques to adjust sampling times of an input signal. The techniques may utilize multi-level modification of the phase of a sampling clock. For example, the level of modification of the phase of...
6970529 Unified digital architecture  
A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive...
6965660 Digital phase-locked loop  
A digital phase-locked loop is provided having a minimal transient recovery time for emitting an output clock signal which is synchronous with a reference clock signal in a normal operating state...
6963629 Adaptive phase locked loop  
A reference signal and a voltage controlled oscillator (VCO) output are compared for relative phase and frequency differences. A lead error signal is generated if the reference signal leads the VCO...
6952462 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector...
6947513 Radio frequency data communications device  
A radio frequency identification device comprises an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter together define an active...
6941116 Linearization technique for phase locked loops employing differential charge pump circuitry  
A differential linear fractional N-synthesizer includes a phase and frequency detection module, a linearized charge pump, a low pass filter, a voltage controlled oscillator, and a fractional N...
6931086 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector...
6928128 Clock alignment circuit having a self regulating voltage supply  
Clock alignment circuits and techniques for reducing power dissipation, increasing power supply noise immunity, decreasing process and temperature variation sensitivity, and providing a wide...
6873670 Automatic pre-scaler control for a phase-locked loop  
A phase locked loop (PLL) system is arranged to automatically adjust the pre-scaler divide ratio. The PLL includes a phase-frequency detector circuit that compares a feedback clock signal to an...
6853696 Method and apparatus for clock recovery and data qualification  
A system for recovering a clock signal from a data signal is described. The system uses an oscillator adapted to generate an oscillator output signal, a first detecting circuit for obtaining a...
6853695 System and method for deriving symbol timing  
A symbol timing derivation system derives receiver timing from received symbols which avoids the need for a pilot tone, thereby reducing power consumption and expanding usable bandwidth. The system...
6847789 Linear half-rate phase detector and clock and data recovery circuit  
Method and apparatus for recovering a clock and data from a data signal. One method of the invention includes receiving the data signal having a first data rate, receiving the clock signal having a...
6829318 PLL synthesizer that uses a fractional division value  
A phase locked loop (PLL) frequency synthesizer has a phase comparator, a voltage-controlled oscillator, a charge pump circuit, a loop filter, a variable frequency divider periodically changing a...
6826248 Phase locked loop circuit  
There is disclosed a phase locked loop circuit comprising a phase frequency comparator configured to output an up/down signal indicating a phase difference and a frequency difference between a...
6819728 Self-correcting multiphase clock recovery  
A method of extracting a clock signal from a data stream, by generating a plurality of multiphase clock signals, creating error signals for each of the multiphase clock signals using the data...
6801585 Multi-phase mixer  
A wireless receiver apparatus including a voltage controller oscillator and mixer. The voltage controlled oscillator generates a first signal having a first frequency, and a second signal having...
6792064 Multiple phase-locked loop circuit  
A multiple phase-locked loop circuit is provided which is capable of being reliably restored from a deadlock state without disturbing normal operations. The multiple phase-locked loop circuit...
6792062 Differential phase-locked-loop circuit  
A differential charge pump with integrated common-mode control circuitry ( 100 ) for a fully differential phase-locked loop is described, having two output lines (OUT + ; OUT − ) and including a...
6778026 High-speed phase frequency detection module  
A high-speed phase-frequency detection module is described to function at very high frequencies and to produce very low jitter. In one embodiment, high-speed phase-frequency detection module...
6771729 Clock recovery circuit and transmitter-receiver therewith  
A clock recovery circuit, according to the present invention, generates a clock signal that continuously maintains a fixed phase to an input data signal. It is made up of a phase comparator, charge...
6760394 CMOS lock detect with double protection  
Method and circuitry for improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device for monitoring the frequency...
6737995 Clock and data recovery with a feedback loop to adjust the slice level of an input sampling circuit  
Techniques that may aid in the recovery of clock and data signals include receiving a stream of incoming data signals and determining an offset based, at least in part, on the state of a transition...
6731712 Fully integrated broadband tuner  
A fully integrated single-loop frequency synthesizer, which can serve as a local oscillator for a broadband tuner, is disclosed, thus allowing the creation of a single-chip solution for broadband...
6727738 Configuration for generating a clock including a delay circuit and method thereof  
A delay locked loop (DLL) employs a gray code (an alternate code) counter as a delay register. Preventing a carry from arising at more than one bit can minimize skipping of delay time...
6721380 Fully differential CMOS phase-locked loop  
The present invention relates in general to integrated circuits, and in particular to method and circuitry for implementing an improved phase-locked loop (PLL) in complementary...
6721377 Method and circuit configuration for resynchronizing a clock signal  
A method for resynchronizing a clock signal, includes the steps of defining a presettable clock signal, dividing a first clock signal having a first frequency with a programmable digital frequency...
6717446 High speed programmable charge-pump with low charge injection  
A high-speed charge-pump circuit includes an array of current source/sinks circuits that are selectable according to UP and DOWN control signals, and a programmable setting. Each current...
6714772 Wireless communication system  
A wireless communication system, which is provided with a PLL circuit having a plurality of oscillators and is capable of processing two or more transmit and receive signal different in frequency...
6710666 Charge pump structure for reducing capacitance in loop filter of a phase locked loop  
A charge pump for reducing capacitance in a loop filter of a phase locked loop. The loop filter contains a resistor and a capacitor. The charge pump includes first and second input current sources...
6704381 Frequency acquisition rate control in phase lock loop circuits  
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) a first reference signal in response to a pump-up signal and (ii) a second...
6683928 Process, voltage, temperature independent switched delay compensation scheme  
A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay...
6674824 Method and circuitry for controlling a phase-locked loop by analog and digital signals  
A mixed-signal-controlled phase-locked loop is provided. This loop includes a mixed-signal-controlled oscillator circuit for generating an oscillating signal having an oscillating frequency and a...
6636575 Cascading PLL units for achieving rapid synchronization between digital communications systems  
A clock synchronization system for synchronizing a first communications device and a second communications device to enable digital communication there between. A first device generates a first...
6594331 Two phase digital phase locked loop circuit  
To provide a high speed digital PLL circuit which is easily manufactured by IC process. The phase of data signal is locked with a first clock of which frequency is the half of the data signal....
6590949 Circuit and method for compensating a phase detector  
A Phase Locked Loop system ( 10 ) provides the signals UP and DOWN for a charge pump ( 14 ). The charge pump ( 14 ) supplies a biasing signal to a voltage controlled oscillator ( 18 ). The phase...
6566920 Phase locked loop using lock detecting circuit  
A PLL (phase locked loop) using a lock detecting circuit includes a phase frequency detector detecting the phase of an input signal and outputting an up signal and a down signal, a lock detecting...
6560306 Phase locked loop (PLL) with linear parallel sampling phase detector  
A parallel sampling phase detector with linear output response. The parallel sampling phase detector for use in data recovery. The device includes a voltage controlled oscillator (VCO) that...
6560305 Frequency detector  
A frequency detection system for producing clock pulses having a frequency equal to the frequency of a stream of binary data. The system includes a voltage controlled oscillator for producing the...
6531927 Method to make a phase-locked loop's jitter transfer function independent of data transition density  
The present invention discloses a novel method and apparatus for making a jitter transfer function of a phase-locked loop independent from the data transition density. The present invention is...
6526111 Method and apparatus for phase locked loop having reduced jitter and/or frequency biasing  
A phase lock loop includes a phase detector, a charge pump circuit, a controlled oscillator, and a jitter control circuit. The control oscillator may also include a biasing circuit to provide the...
6526109 Method and apparatus for hybrid smart center loop for clock data recovery  
Modern fiber optic networks typically transfer data using encoding in which the clock is transmitted along with the data, for example in NRZ format. In order to use the clock to process the data,...
6522204 Phase-locked loop for ADSL frequency locking applications  
A phase-locked loop (PLL), particularly useful for ADSL frequency locking applications, uses inexpensive external components in combination with versatile logic that can be implemented in a...
6483886 Phase-locked loop circuitry for programmable logic devices  
A phase-locked loop circuit (“PLL”) is adjustable in both phase and frequency. By providing a plurality of taps on the voltage-controlled oscillator of the PLL, and providing separate...
6470060 Method and apparatus for generating a phase dependent control signal  
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector...
Matches 51 - 100 out of 237 < 1 2 3 4 5 >