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7616721 |
Apparatus and method for checking network synchronization clock signal in communication system
In an apparatus and method for checking a network synchronization clock signal in a communication system, the apparatus generates a divided clock signal which is the same as an externally inputted...
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7616708 |
Clock recovery circuit
A clock recovery circuit comprising an initial delay select circuit, a delay locked loop and a clock synthesizer circuit is provided. The initial delay select circuit comprises an initial timing...
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7613254 |
Phase detector for comparing phases of data and a plurality of clocks
A phase detector that compares the phases of data and four-phase first to fourth clocks having a half rate of the data and being 90° out of phase with one another. Exemplary embodiments of the...
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7613237 |
Built-in test feature to facilitate system level stress testing of a high-speed serial link that uses a forwarding clock
A method of ensuring robust operation of a differential serial link is provided. The method provides a first integrated circuit having 1) a phase generator constructed and arranged to provide a...
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7609796 |
Communication control apparatus and a method for freely controlling the transmission of time slots
A communication control apparatus includes a signal receiver for receiving a state variable signal indicating a timing of data transmission from a neighboring node. The apparatus also includes a...
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7609102 |
Pattern-dependent phase detector for clock recovery
A phase detector apparatus and method used for clock recovery from a data signal is provided. The phase detector provides phase correction signals to a clock signal generator, where the phase...
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7606343 |
Phase-locked-loop with reduced clock jitter
The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a...
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7606340 |
Phase detection device and method thereof
A phase detection device comprising an analog-digital converter, an interpolator, and a determining unit. The analog-digital converter receives an analog signal and converts the analog signal to a...
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7599461 |
Method and apparatus for generating one or more clock signals for a decision-feedback equalizer using DFE detected data in the presence of an adverse pattern
Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data, in the presence of an adverse pattern, such as a Nyquist...
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7599460 |
Transmitting apparatus
A device including a line interface for additionally installing a line is installed in a terminal repeater device which takes a work and protection redundancy configuration based on a criterion...
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7593499 |
Apparatus and method for low power routing of signals in a low voltage differential signaling system
A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit...
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7593498 |
Method and apparatus for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications
Methods and apparatus are provided for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications. An interface is provided for use...
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7590387 |
High accuracy voltage controlled oscillator (VCO) center frequency calibration circuit
Methods and systems for calibrating a frequency of a circuit are disclosed herein and may comprise dividing a feedback frequency of an output frequency signal to generate a divided frequency...
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7590212 |
System and method for adjusting the phase of a frequency-locked clock
A clock signal regeneration system and method to adjust the phase of a frequency-locked clock signal is provided. The system includes a numerically controlled oscillator, a clock source, and an...
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7587014 |
Digital frequency/phase recovery circuit
A digital frequency/phase recovery circuit includes a comparator with hysteresis, a counter, a frequency determiner, a multi-phase clock generator, a transition detector, a phase adjuster, and a...
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7583774 |
Clock synchroniser
A clock synchronizer, for generating a local clock signal synchronized to a received clock signal, is described and claimed, along with a corresponding clock synchronization method. The clock...
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7580498 |
Closed loop control system and method of dynamically changing the loop bandwidth
The invention provides a method for dynamically changing the loop bandwidth of a closed loop control system. At least one loop bandwidth parameter controls the loop bandwidth of the closed loop...
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7580496 |
Device for receiving series data
A circuit for receiving digital data arriving in series comprising a circuit for generating a reference dock and a circuit for oversampling the received data memorizing the samples sampled at the...
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7580491 |
Quarter-rate clock recovery circuit and clock recovering method using the same
A quarter-rate clock recovery circuit includes a clock generator, a phase interpolation unit, a phase detector, and a controller. The clock generator generates first through fourth clocks having a...
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7577225 |
Digital phase-looked loop
Embodiments of the invention include an integrated circuit including a phase-locked loop (PLL). The integrated circuit includes a phase detector, a frequency detector, a loop filter, a...
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7577224 |
Reducing phase offsets in a phase detector
In one embodiment, the present invention includes a system having an amplifier to receive an incoming signal and a recovery circuit coupled to the amplifier that includes a phase detector to adjust...
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7573968 |
Data transmission circuit with serial interface and method for transmitting serial data
A data transmission circuit includes a first clock generating circuit that generates a first clock; a second clock generating circuit that generates a second clock, which is different from the...
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7570727 |
Data transmission controller and sampling frequency converter
In a data transmission controller apparatus, a first-in first-out storage stores newly inputted data in response to a write request signal, and reads and outputs the stored data which has been...
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7570721 |
Apparatus and method for multi-phase digital sampling
A method and apparatus for determining a relationship between an input signal frequency and a reference signal frequency is envisioned. The system derives a plurality of internal reference signals...
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7567643 |
Phase lock loop device
A phase lock loop device further includes a probability shaping device provided between a phase detection device and charge pump and loop filter (CPLF) device. The probability shaping device...
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7567642 |
Phase detector with extended linear operating range
A method and apparatus for extending the linear range of a phase detector. In one embodiment, a limited range phase difference is generated between selected edges of first and second input signals,...
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7567633 |
Reception device with data recovery mechanism, adapted to transmission system using a direct spread spectrum sequence
A BPSK type reception device that includes a decoder for decoding a digital input signal, first and second comparators for delivering a decoded data signal and a data capture clock signal also...
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7561653 |
Method and apparatus for automatic clock alignment
The present invention synchronizes signals generated and used in different clock domains. The invention is applicable to a CDR circuit in which phase adjustment of a multiphase clock to the phase...
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7561652 |
High frequency spread spectrum clock generation
For EMI reduction the current modulation profile is preferably used for frequencies over 1 GHz while the frequency deviation is increased at least to ±2.5 MHz and the modulation frequency is...
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7561651 |
Synchronization of a data output signal to a clock input
A method for synchronizing an output signal of a device phase aligned with an input clock includes the steps of providing an oscillator signal having a period Πn of 1/(f 1 *2 n ), wherein f 1 is...
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7561582 |
Data reception device
A data reception device having a reception data buffer unit storing a plurality of packets contained in a data packet, a reception data amount measuring unit measuring the data amount stored in the...
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7558357 |
Systems and methods for reducing frequency-offset induced jitter
Methods and apparatus nullify an intrinsic jitter component in a digital clock recovery circuit induced by a time base frequency difference between an incoming data signal and a local...
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7555085 |
CDR algorithms for improved high speed IO performance
A data receiver system. The system includes a clock generator configured to output a reference clock and circuitry configured to measure a direction of a phase difference between an input data...
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7555073 |
Automatic frequency control loop circuit
Provided is a frequency control loop circuit changing division ratios of a frequency synthesizer to oscillate frequencies in a broadband with high precision. The circuit comprises a clock...
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7554373 |
Pulse width modulation circuit with multiphase clock
In a pulse width modulation circuit, a multiphase clock generation section generates a multiphase clock signal according to a reference clock. Then, a pulse width modulation signal is generated...
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7551651 |
Method and system for time domain multiplexers with reduced inter-symbol interference
Method and system for a high-speed multiplexer with reduced inter-symbol interference are disclosed. In one embodiment of the present invention, two input bit streams are interleaved by a...
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7545898 |
System and method for clock rate determination
Presented herein are systems and methods for clock rate determination. A bitstream is sampled by sampling a transmitted clock signal at a rate corresponding to a receiver clock signal, and...
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7542535 |
Method and apparatus for recovering a clock signal
A method includes receiving a serial data signal including a preamble and an embedded clock signal having an embedded clock signal frequency, and processing the preamble using logic to determine...
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7538706 |
Mash modulator and frequency synthesizer using the same
A MASH modulator. The MASH modulator receives a fractional input value, generates an integer output value, and comprises three cascaded first order sigma delta modulators (SDMs) each comprising an...
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7535981 |
Clock generation circuit and method thereof
The present invention generates an output clock signal CLKreq having a frequency freq between the frequency fref/A of a divided clock signal CKL 1 and the frequency fref/(A+1) of a divided clock...
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7532696 |
Calibration device for a phased locked loop synthesiser
A calibration device for a phase locked loop arranged to generate an output frequency based upon a first frequency range of an input signal applied to a first input and a second frequency range of...
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7532695 |
Clock signal extraction device and method for extracting a clock signal from data signal
A clock signal extraction device for extracting a clock signal from a periodic data signal includes a phase detector for detecting a first phase difference between rising edges of said data signal...
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7529331 |
Wobble clock generator and driving method thereof
A wobble clock generator with a protective mechanism that can avoid interference generated from a phase-modulated wobble signal. The wobble clock generator has an arithmetic/logic circuit and a...
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7529329 |
Circuit for adaptive sampling edge position control and a method therefor
A clock and data recovery circuit (CDR) for receiving high-speed digital data, and having an analog phase offset control capability, is improved by providing an adaptive sampling edge position...
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7526056 |
Delay locked loop with low jitter
Digital delay locked loops which generate fixed angle delayed (e.g., quadrature) clock signals based on a reference clock signal and that accounts for clock signal delay. The number of quadrature...
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7526049 |
Data sampling circuit and semiconductor integrated circuit
A data sampling circuit has a receiver which receives an embedded clock obtained by multiplexing a clock signal and data, a phase comparator which outputs a phase difference signal by performing a...
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7522688 |
Wireless clock system and method
A wireless clock system includes a master clock or other master time source, and a plurality of slave clocks or repeater devices. Each slave clock can both wirelessly receive and wirelessly...
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7522686 |
CMOS burst mode clock data recovery circuit using frequency tracking method
Provided is a burst mode clock data recovery circuit for extracting clock information and data information from transmitted data to process data synchronized with clock. The circuit includes a...
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7519140 |
Automatic frequency correction PLL circuit
An automatic frequency correction phase-locked loop (PLL) circuit includes an analog control circuit and a digital control circuit. The digital control circuit includes a High-side comparator and a...
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7519113 |
Noise detection device
Noise detection is performed by using the output of the phase comparator that the PLL comprises. The phase comparator outputs a signal that is based on the phase difference between the output of...
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