Matches 401 - 450 out of 724 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
5982831 Feed forward method and apparatus for generating a clock signal  
A feed forward apparatus and method discipline a clock signal by a reference signal in digital telecommunication networks. A synthesizer correction term within the feed forward apparatus and method...
5982834 Clock recovery system for high speed small amplitude data stream  
A clock recovery system that allows recovery of a clock signal from a high speed, potentially small amplitude data stream. The invention uses a normally avoided property of a non-linear oscillator...
5969631 Method and control system for the synchronized transmission of digital data  
In a method and system for transmitting digital data, a data acceptance clock signal generator that has a controllable clock frequency in a peripheral module is correspondingly adapted to clock...
5963607 Direct digital synthesizer with high resolution tracker  
A chirp direct digital synthesizer is formed with a phase and frequency tracker circuit to provide both enhanced resolution and reduced power consumption. The phase and frequency tracker circuit...
5963608 Clock extractor for high speed, variable data rate communication system  
To derive a clock embedded in a digital data stream, a variable data rate synchronizer includes a data rate estimator that derives an estimate of the data rate of data contained in the digital data...
5945855 High speed phase lock loop having high precision charge pump with error cancellation  
A high precision charge pump used in a phase-lock loop incorporating a type-IV phase/frequency detector is designed and constructed to substantially eliminate the effects of ringing and glitch...
5943379 Multi-phase trapezoidal wave synthesizer used in phase-to-frequency converter  
A trapezoidal waveform synthesizer converts a digital phase error signal into a plurality of phase-separated trapezoidal analog waveforms. The trapezoidal waveform synthesizer includes an up/down...
5943378 Digital signal clock recovery  
A clock recovery circuit for recovering a symbol clock (226) includes a level decoder (210) for determining one of a plurality of received states of a demodulated signal (105) during each symbol...
5940435 Method for compensating filtering delays in a spread-spectrum receiver  
A method for configuring the receiver with an IF delay value that indicates the timing of symbol transitions in a received signal processed by the receiver. The receiver recovers a timing that has...
5937021 Digital phase-locked loop for clock recovery  
The invention relates to a phase-locked loop delivering a recovered clock signal from a reference clock signal F ref in which some transitions are missing. The loop includes a first divide-by-M...
5937020 Digital information signal reproducing circuit and digital information system  
Digital information including a sync data field and a user data field subsequent thereto is read from a storage media as a digital information signal in an analog signal format. The obtained signal...
5923704 Transmit clock generation system and method  
A method for generating transmit clock timing of a first communications unit of a communications system. The communications system includes the first communications unit and a second communications...
5920556 Frequency modulation using a phase-locked loop  
A transmitter transmitting signal bursts to a TDMA communication system, and comprising a frequency synthesizing circuit having an input on which a bit flow is received, and an output on which a...
5909473 Bit synchronizing circuit  
In a bit synchronizing circuit, the oscillating operation is prevented in the phase synchronizing stage such that even the reception data including a phase variation such as a jitter component can...
5901190 Digital delay locked loop circuit using synchronous delay line  
A digital locked loop circuit having a synchronous delay line, an input node for receiving an external clock signal, and an internal clock node for generating an internal clock signal synchronized...
5889824 Intermittent receiving apparatus capable of reducing current consumption  
In an intermittent receiving apparatus (10) for intermittently receiving a carrier signal having a carrier frequency (f R ) and carrying data as an intermittent received carrier signal so as to...
5878088 Digital variable symbol timing recovery system for QAM  
A receiver is arranged for receiving a transmitted quadrature amplitude modulated (QAM) signal representing successive symbols, and including an in-phase (I) component and a quadrature (Q)...
5875219 Phase delay correction apparatus  
A digital delay locked loop (DLL) includes a phase detector for outputting a comparing signal by comparing a system clock signal with a chip clock signal, a shift register for sequentially shifting...
5872821 Arrangement for generating digital signals  
Recurring digital control signals are provided in a predeterminable time frame, with a high time-dependent resolution and flexibility. Data for the control signals are stored in a write/read memory...
5870442 Timing recovery arrangement  
Timing recovery circuits, automatic gain control circuits and the like, employ a so-called vector tracking filter (VTF) in conjunction with other timing recovery techniques. The VTF includes a...
RE36090 Method and a device for synchronizing a signal  
A device synchronizes an internal signal with respect to a reference signal, each signal comprising pulses normally occurring at a rated frequency. The device uses a phase comparator to analyze the...
5848109 Apparatus and process for sampling a serial digital signal  
A process and apparatus for sampling a serial digital signal (D), which includes phasing of the digital signal with a clock signal (C) and sampling the digital signal at delayed instants (Si),...
5844954 Fine resolution digital delay line with coarse and fine adjustment stages  
A device and method for reducing phase jitter in digital phase locked loop applications resulting in smaller clock skews between application specific integrated circuits (ASICs). Phase jitter is...
5841823 Method and apparatus for extracting a clock signal from a received signal  
A clock signal is extracted from a received signal. An edge detector detects edges of the received signal, where the received signal transitions between a logic 0 and a logic 1. A center between...
5822386 Phase recovery circuit for high speed and high density applications  
A phase recovery circuit consists of a tapped delay line created by a string of inverters where taps are taken at every other inverter. To initialize the circuit, each tap loads a signal sample...
5818890 Method for synchronizing signals and structures therefor  
A serial data signal is synchronized to a clock signal in a synchronization circuit (10). Synchronization is accomplished by generating a plurality of delayed versions of the serial data signal...
5815541 Digital phase locked loop assembly  
A digital PLL apparatus includes a synchronization integrating circuit, an angle calculating circuit, and a digital PLL circuit. The synchronization integrating circuit determines a symbol timing...
5802461 Apparatus and method for timing recovery in vestigial sibeband modulation  
Apparatus and method (10) for recovering timing information from a vestigial sideband (VSB) modulated signal generate a left hand component signal and a right hand component signal from the...
5790612 System and method to reduce jitter in digital delay-locked loops  
The present invention incorporates a variable delay circuit to add delay to a clock signal. In a preferred embodiment of the present invention, the delay is determined and fixed by a circuit...
5787135 Variable frequency divider  
A phase locked loop includes a voltage controlled oscillator (VCO) for generating output VCO pulses. A frequency divider divides the VCO pulses by a variable number to produce frequency divided...
5781054 Digital phase correcting apparatus  
The present invention relates to a digital phase correcting apparatus, including a phase comparator (100), a loop filter (110), and a digital controlled oscillator (120). The digital controlled...
5778217 Parallel signal processing device for high-speed timing  
A parallel signal processing device for high speed timing recovery in a high speed transfer network includes a plurality of data sampling processors (DSP), a central phase-error processor (CPP),...
5774510 First-order loop control configuration for a phase-rotator based clock synchronization circuit  
An embodiment of the present invention is electronic circuitry for producing an I-phase quadrant pointer (FI) and a Q-phase quadrant pointer (FQ) by sampling a feed clock (IC) and a quadrature feed...
5774508 Data synchronizer phase detector and method of operation thereof  
In a data synchronizer a timing error estimator samples a received stream of digitized data symbols at the beginning, end, and a mid-point of a symbol period. These samples are used with a model...
5771264 Digital delay lock loop for clock signal frequency multiplication  
A digital delay lock loop for generating frequency multiples of an input clock signal includes a programmable digital oscillator, a phase comparator, a programmable counter and delay control logic....
5768326 PLL circuit and method  
A PLL circuit for use in a digital broadcasting receiver includes a receiver for receiving a bit stream containing program clock references (PCRs) transmitted from a broadcast station. The PCRs...
5761242 System for the measurement of sonet network synchronization quality  
The invention provides a system for measuring the synchronization of SONET signals. The invention counts the bits in an STS-1 signal starting at a reference time point and ending when the framing...
5761255 Edge-synchronized clock recovery unit  
A clock recovery unit for recovering a clock embedded in a data communication is disclosed. The clock recovery unit includes an oscillator (50) operating at a frequency close to that of the clock...
5757873 Differential delay buffer  
A differential delay buffer includes a variable delay buffer unit, the variable delay buffer unit having a differential stage followed by a variable hysteresis stage. A plurality of variable delay...
5754607 Method and apparatus for achieving fast phase settling in a phase locked loop  
A method and an apparatus are provided to achieve fast phase settling when a reference signal for a phase locked loop changes from a first frequency to a second frequency, such as during holdover...
5754606 Clock signal regenerating circuit  
A clock signal regenerating circuit is provided for use in a receiver for receiving a burst signal or packet signal which is intermittently transmitted in digital radio communications, wherein a...
5754437 Phase measurement apparatus and method  
A phase measurement apparatus and method for measuring electrical signal jitter and wander operates in real time and digitally controls bandwidths over which the measurements are performed. The...
5742650 Power reduction method and apparatus for phase-locked loop based clocks in a data processing system  
A method and apparatus for reducing power associated with acquiring phase-lock between a reference clock signal and an internal clock signal after each exit from a quiescent state by a data...
5737371 Realignment of data stream from an optical disk  
An apparatus and method are provided for detecting and correcting data stream misalignments during read back of data in an optical drive unit. In a dual PLL system, after a data stream is divided...
5737374 Delay locked loop for use in a GPS signal receiver  
Delay locked loop intended to be used in a receiver of signals emitted by a GPS satellite, comprising a pseudo-random code generator (35), a local oscillator (34), a modulator (14) for modulating...
5737370 Method for initializing a network  
A method for initializing a network for data transmission between a plurality of subscribers being connected to one another in ring-like fashion, includes sending a clock signal through the network...
5731723 Half symbol delay calibration for phase window centering  
The present invention provides a method and apparatus for half symbol delay calibration for phase window centering. To perform calibration of phase window centering, a carefully designed input...
5732109 Phase detector  
Disclosed is a phase detection apparatus for accurately calculating the phase of an input digital complex baseband signal point independently of its amplitude value, without requiring any...
5715281 Zero intermediate frequency receiver  
A zero intermediate frequency radio receiver that comprises mixing stages, an A to D converter, a digital demodulator, a carrier tracking system and a carrier nulling system is disclosed. The...
5712883 Clock signal distribution system  
A system for distributing synchronous clock signals includes a set of spatially distributed deskewing stages. Each stage includes matching adjustable first and second delay circuits and a phase...
Matches 401 - 450 out of 724 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >