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5463655 Single-ended pulse gating circuit  
The present invention provides a gating circuit having two separate paths for detecting even and odd bits. Each path includes an equal number of coupled flip-flops. After bit detection,...
5459766 Digital phase-locked loop  
An integrated circuit comprises a time-discrete oscillator which generates numerical and time-discrete phase values of an oscillator signal. The circuit also comprises a time-continuous oscillator...
5457719 All digital on-the-fly time delay calibrator  
An on-chip digital servo scheme for providing continuous calibration of integrated circuit on-chip time delay devices to provide real-time regulation against various parameter or environmental...
5457423 Radio data signal demodulator with clock signal recovery  
For a demodulator for radio data signals, where transmission of these signals is carried out through phase shifting of a suppressed subcarrier, where a multiplex signal, which contains a signal...
5457718 Compact phase recovery scheme using digital circuits  
The present invention is a fully integrated digital filter which interacts with a phase comparator to provide a phase lock loop and data retiming function. The digital filter includes a prescaler,...
5455847 Clock recovery phase detector  
A phase detector for symbol clock recovery in a digital communications system determines the phase error of a local symbol clock from the symbol rate of a transmitted signal by sampling the...
5452324 Packet data recovery system  
An improved data sampling system for sampling data transmission in a computer system includes a reference clock, a delay locked loop circuit, a packet enable circuit, a delayed selector control...
5448598 Analog PLL clock recovery circuit and a LAN transceiver employing the same  
A VSLI transceiver chip incorporating an improved analog PLL circuit for recovering a digital clock signal from a digital data signal having pulse widths which may vary during each data cycle. The...
5446766 Digital communication systems  
This invention relates to a clock synchronisation circuit and a method of synchronising a clock signal with a received data signal in a digital communications system such as a burst-mode TDMA...
5436943 Digital audio signal processing circuit  
A digital audio signal processing circuit for eliminating the amplitude and phase components of logic induced modulation from a left right clock signal, a bit clock signal and digital data bits...
5430773 Data sampling apparatus, and resultant digital data transmission system  
The apparatus for sampling data recurring with a period (R) in the data signal (TS) includes a phasing circuit (43) that adjusts the delay of a clock signal with respect to one edge of the data...
5428648 Digital PLL circuit having signal edge position measurement  
A ring oscillator has its inverter states in respective inner stages change at a time unit longer than a period of a master clock MCK and is oscillated at a period longer than the period of the...
5420895 Phase compensating circuit  
A phase compensating circuit in a video signal processing system utilizing a frequency folding technique which requires the recovery of an exact sampling phase is disclosed. A predetermined pattern...
5416805 Receiver for receiving frequency modulated signals and having a controlled acquisition band  
A receiver for receiving frequency modulated signals and having a controlled acquisition band, the receiver including: a phase-locked loop (PLL) demodulator (40); a frequency translation circuit...
5412698 Adaptive data separator  
An adaptive data separator for detecting systematic differences between the arrivals of the rising and falling edges of a digital signal and for compensating for the difference. Data packets from a...
5402453 Apparatus and method for reliably clocking a signal with arbitrary phase  
A clocking circuit and method for phasing a signal with an unknown phase to a clock signal includes a time requirement duration (TRD) signal which has two states and the duration of one of the...
5396523 Shifting the phase of a clock signal, in particular for clock recovery of a digital data signal  
The invention relates to a clock recovery for a digital data signal. A phase detector receives the data signal and transmits it after clock recovery. A phase correcting device creates and...
5394443 Multiple interval single phase clock  
A multiple phase clock distribution system for allowing a circuit load to be clocked on predetermined phases of a single clock signal is provided. A single phase clock is the triggering signal for...
5377233 Seam-less data recovery  
A circuit for seamlessly printing data from a remote source that is arriving at a clock rate that is equal to the clock rate of the local data, but that has a different clock phase, due to the...
5371766 Clock extraction and data regeneration logic for multiple speed data communications systems  
Clock extraction and data regeneration logic is provided for a multiple rate digital data communications system such as a local area network (LAN). The logic is implemented in adapters which...
5371765 Binary phase accumulator for decimal frequency synthesis  
A direct digital synthesizer of the phase-accumulator type, constructed entirely of binary-radix digital hardware, generates signals with decimally-defined frequency resolution. The synthesizer is...
5369672 Interface circuit capable of performing exact data transfer  
An interface circuit capable of performing an exact data transfer between two devices operated by asynchronous two clocks of the same frequency even when the clock contains a jitter, including...
5329559 Phase detector for very high frequency clock and data recovery circuits  
A phase detector circuit, used in a very high frequency phase-locked loop, receives an incoming NRZI data stream and a phase-locked loop clock signal. For each data transition in the received data...
5311560 Frequency synthesizer  
A frequency synthesizer which can effect a high speed frequency hopping operation without causing deterioration in stability in phase and frequency in a phase frequency-locked condition and also in...
5307342 Heterogeneous ports switch  
A communication switch having heterogeneous ports. The heterogeneous ports are connected to nodes which may be operating at different frequencies and which may have different optical...
5307382 Lock apparatus for dual phase locked loop  
Lock apparatus for a dual PLL which is capable of detecting a locked state of a receiving frequency as well as a locked state of a transmitting frequency. The dual PLL lock apparatus comprises a...
5301210 Coherent demodulating device with carrier wave recovering digital circuit  
A coherent demodulating device is characterized by a demodulating circuit and a carrier recovering circuit produced entirely in digital form. Two quadrature demodulation carrier waves produced by a...
5301196 Half-speed clock recovery and demultiplexer circuit  
A clock recovery circuit and demultiplexer circuit which operate at half the data rate of a received data stream. The half-speed clock recovery circuit generates a 0 and 90-degree clock at half the...
5297181 Method and apparatus for providing a digital audio interface protocol  
A digital audio interface protocol carries multiple channels of digital audio information serially between a transmitting digital audio tape recorder and a plurality of receiving recording units....
5297185 Pattern detection and synchronization circuit  
For identifying a preamble or other pattern in a binary bit stream, containing data coded to have a different average number of ones to zeroes from the pattern in question, a pattern detection...
5294842 Update synchronizer  
An update synchronizer includes a two-stage synchronization unit for generating enable signals to select an output signal from among multiple input clock signals of a clock delay multiplexer. The...
5280501 Data bit synchronization  
Bit synchronization is achieved by identifying potential bit sample points and assigning corresponding weight values as a function of signal noise vulnerability. The greater the possibility of...
5253254 Telecommunications system with arbitrary alignment parallel framer  
A high-speed communication system (32) comprises a serial-to-parallel converter (38) for arbitrary converting a stream of serial data to a stream of arbitrarily aligned parallel data. A pattern...
5235596 Circuit arrangement for generating synchronization signals in a transmission of data  
In a transmission of data upon employment of binarily coded data signals (D), reception clocks (ET) with which the data signals (D) are sampled in their middles are generated for the recovery of...
5233636 Analog and digital phase detector for bit synchronism  
The present invention provides a phase detector comprising a driver U1 and D-type flip-flops U2 and U3 which reduces the high frequency component of the jitter in VCO, in analog-fashion operation,...
5230012 Process and circuit arrangement for digital control of the frequency and/or phase of scanning clock pulses  
Scanning samples of digital signals received in analog form are sent at intervals determined by the scanning clock pulses to a digital signal receiving network after analog-digital conversion for...
5230013 PLL-based precision phase shifting at CMOS levels  
A circuit for generating precise, phase shifted, CMOS level output signals with respect to an input data signal has been provided. The circuit utilizes a phase-locked loop for generating a precise...
5212716 Data edge phase sorting circuits  
Data edge phase sorting circuits for communication systems and information and data processing systems employing digital phase locked logic circuits. The sorting circuits phase sort edge...
5197086 High speed digital clock synchronizer  
A synchronization system for locking a data input signal to a local clock uses the data input signal to provide the timing for capturing phase waveforms generated by a delay element string and a...
5185768 Digital integrating clock extractor  
A digital integrating clock extraction technique for communication systems and information and data processing systems having high jitter and/or noise is disclosed. The technique is based on the...
5182761 Data transmission system receiver having phase-independent bandwidth control  
A data transmission system receiver is disclosed which receives a formatted data stream (302) and operates in one of at least a first bandwidth mode and a second bandwidth mode. The formatted data...
5173927 Frequency detector system on a digital phase locked loop  
A frequency detection system is based on a digital phase locked loop, the detection system being especially suitable for use in noisy environments like supervisory audio tone (SAT) detection in...
5161173 Method of adjusting the phase of a clock generator with respect to a data signal  
In a method of adjusting the phase of a clock generator with respect to a data signal (50) an auxiliary signal (52) is generated by comparing the data signal (50) and a clock signal (51). The...
5151927 Dual-mode synchronization device, in particular for frame clock phase recovery in a half-duplex transmission system  
A dual-mode synchronization device is designed in particular to recover the phase of the frame clock in a half-duplex transmission system. It is included in a receiver in a half-duplex digital...
5146478 Method and apparatus for receiving a binary digital signal  
The reception of the binary digital signal that may also have phase shifts should be accomplished with a supplied clock that has an arbitrary phase relation compared to the digital signal and can...
5138635 Network clock synchronization  
In a network including an exchange having a masterclock and a number of subscriber stations connected to the exchange, the exchange includes a delay line which receives incoming data. Samples are...
5136614 Spread spectrum communication system  
A spread spectrum communictdion system includes a transmitter and a receiver, and an on-off keying signal is inputted to the transmitter. A carrier signal is modulated by the on-off keying signal,...
5134637 Clock recovery enhancement circuit  
An improved clock recovery enchancement circuit is provided that is particularly adapted for solving the problem caused by an incoming signal that is asymmetric and comprises a sub-harmonic tone of...
5131014 Apparatus and method for recovery of multiphase modulated data  
A method and apparatus are provided for recovering multiphase modulated data. A signal pulse of a fixed duration is generated upon the transition of a first phase component of a multiphase...
5128970 Non-return to zero synchronizer  
A non-return-to-zero synchronizer is described which creates an output pulse signal that is synchronized to a system clock signal, from an asynchronous input strobe signal which can occur at any...
Matches 501 - 550 out of 722 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >