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7620138 Apparatus for receiving parallel data and method thereof  
A data reception apparatus adjusts a first clock signal and fetches the data signal in a data buffer, using a data signal in accordance with the adjustment clock signal in such a way that a set-up...
7620137 System and method for clock drift correction for broadcast audio/video streaming  
A clock rate used in rendering broadcast streaming audio/video data is adjusted to converge on a clock rate associated with broadcasting the streaming data. The clock rate is adjusted by monitoring...
7619547 Serial-to-parallel converter circuit and liquid crystal display driving circuit  
A serial-to-parallel converter circuit comprising: an m-bit serial data holding unit to be input with serial data whose input bit number is set to m or n (<m) bits within a transfer period and a...
7613211 Digital clock smoothing apparatus and method  
A method for digital clock smoothing comprising: (A) inputting an asynchronous data stream having an asynchronous symbol rate into a two-port memory block; (B) accumulating a plurality of symbols...
7602875 Sampling rate conversion method and apparatus  
A sampling apparatus for converting first data, sampled at a first sampling rate, into second data, sampled at a second sampling rate. A FIFO storing the first data based on a write control signal...
7599459 Receiving apparatus, data transmission system and receiving method  
A receiving apparatus receives data sequences, each of which includes plural data blocks, from plural transmission lines, respectively. The apparatus includes plural elastic buffers and a deskew...
7593499 Apparatus and method for low power routing of signals in a low voltage differential signaling system  
A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit...
7593498 Method and apparatus for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications  
Methods and apparatus are provided for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications. An interface is provided for use...
7590152 Router-based monitoring of EF-on-EF jitter  
A system for monitoring EF-on-EF jitter in a network node having an EP output queue into which EF packets are entered comprises a first counter that counts the packets entering the queue and also a...
7583774 Clock synchroniser  
A clock synchronizer, for generating a local clock signal synchronized to a received clock signal, is described and claimed, along with a corresponding clock synchronization method. The clock...
7583772 System for shifting data bits multiple times per clock cycle  
A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following...
7571338 Determining a time difference between first and second clock domains  
Buffer circuitry receives data to be processed by electronic circuitry using a first clock signal associated with a first clock domain. The buffered data is output using a second clock signal...
7570727 Data transmission controller and sampling frequency converter  
In a data transmission controller apparatus, a first-in first-out storage stores newly inputted data in response to a write request signal, and reads and outputs the stored data which has been...
7567643 Phase lock loop device  
A phase lock loop device further includes a probability shaping device provided between a phase detection device and charge pump and loop filter (CPLF) device. The probability shaping device...
7526017 Transmitting device, receiving device, transmission system, and transmission method  
A transmitter LSI 1 transmits a source clock, transmission data, and a transmission sync signal indicating the timing of the transmission data to a receiver LSI for establishing transmission...
7522898 High frequency synthesizer circuits and methods  
Embodiments of the present invention include a frequency synthesizer comprising a first plurality of dividers receiving a first signal having a first frequency and generating a first plurality of...
7515671 Method for correcting jitter of transmission data  
Data is transferred from a transmitter to a data buffer of a receiver according to the clock of the transmitter. When the amount of data in the data buffer exceeds an upper limit, the frequency of...
7515652 Digital modulator for a GSM/GPRS/EDGE wireless polar RF transmitter  
A digital modulator in a radio transmitter includes circuitry for switching between Gaussian Minimum Shift Keying (GMSK) and Phase-Shift Keying (PSK) while maintaining spectral mask requirements....
7512203 Data cleaning with an asynchronous reference clock  
Embodiments of the present invention may provide for independent setting of jitter tolerance and jitter transfer levels, and reduced jitter generation of a data transmission device, such as a clock...
7508895 Oversampling apparatus, decoding LSI chip, and oversampling method  
An oversampling system (oversampling apparatus), a decoding LSI chip, and an oversampling method capable of decreasing the memory capacity of an output buffer used to oversample and output decoded...
7500044 Digital phase relationship lock loop  
In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input...
7499516 Methods and apparatus for interface buffer management and clock compensation in data transfers  
A circuit for data stream buffer management, lane alignment, and clock compensation of data transfers across a clock boundary using a first in first out (FIFO) buffer in each serial channel is...
7496167 Storage efficient sliding window sum  
A delay buffer includes a first shift register receiving input data and having a shift signal input port. The first shift register right shifts the input data responsive to a shift signal on the...
7480360 Regulating a timing between a strobe signal and a data signal  
A technique includes in response to a training mode, communicating between a device and a processor of a computer system over a data bit line of a bus. The technique includes based on the...
7472199 System and method for receiving data at a first rate and adapting the data for being transported at a second rate  
Systems and methods for transporting client data received at a first rate over an interconnect at a second, higher rate, wherein the client data is combined with dummy data according to a pattern...
7469356 Signals crossing multiple clock domains  
Methods, systems, and circuits are provided for signals crossing multiple clock domains. One circuit includes a number of different clock domains located on different portions of the ASIC. A number...
7466723 Various methods and apparatuses for lane to lane deskewing  
Various methods, apparatuses and systems are described in which a skew delay time between communication lanes is determined. A data transfer path is established which includes two or more...
7460630 Device and method for synchronous data transmission using reference signal  
A data transmitter and a data receiver generate respective synchronous signals from a common reference signal. The data receiver adjusts a phase of a first clock signal using each one of one-bit...
7460629 Method and apparatus for frame-based buffer control in a communication system  
A method and apparatus are disclosed for controlling a buffer in a digital audio broadcasting (DAB) communication system. The decoder buffer level limits are specified in terms of a maximum number...
7460619 Method and system for optimizing coding gain  
A method and system for optimizing coding gain that alters the backsearch buffer length and/or the input buffer length of a decoder in response to one or more transmission performance...
7457390 Timeshared jitter attenuator in multi-channel mapping applications  
A timeshared data tributary mapping system and method are provided for mapping information into Synchronous Payload Envelopes (SPEs). The method buffers data from a plurality of tributaries and...
7450678 Asynchronous signal input apparatus and sampling frequency conversion apparatus  
In an asynchronous data input apparatus, a writing section writes data successively into a FIFO buffer memory at an variable input rate so that the data are accumulated in the FIFO buffer memory. A...
7443940 Alignment mode selection mechanism for elastic interface  
Methods and apparatus are disclosed for aligning received data bits in elastic interface systems. Depending upon which one of several alignment modes is selected, data bits can be loaded into FIFO...
7440532 Bit slip circuitry for serial data signals  
Circuitry for use in aligning bytes in a serial data signal (e.g., with deserializer circuitry that operates in part in response to a byte rate clock signal) includes a multistage shift register...
7440531 Dynamic recalibration mechanism for elastic interface  
A method and apparatus for de-skewing and aligning digital data received over an elastic interface bus is disclosed. Upon receiving the data, it is sent through a programmable delay line. While in...
7436918 Output stage synchronization  
Systems and methods for transferring data across clock domains in a manner that avoids metastability of the data and is very tolerant of variations in the clock signals of the different clock...
7428288 Asynchronous transport stream receiver of digital broadcasting receiving system employing DVB-ASI mode and method for transmitting asynchronous transport stream thereof  
An asynchronous transport stream receiver of a digital broadcasting receiving system connected to MPEG-2 (Moving Picture Experts Group-2) equipment, such as a VOD (Video On Demand) server is...
7428287 Method and device for synchronizing data transmission between two circuits  
For synchronising the data transmission between a CMOS circuit ( 1 ) and a bipolar circuit ( 2 ) a DLL (delayed lock loop) is provided which sets a phase deviation between the operating clocks (CLK...
7424059 Data transfer circuit  
A transmission unit loads transmission data on a first register and outputs it to a transfer line and starts counting the transmission clock signals in a strobe generation counter according to a...
7414560 Wireless communication system including an audio underflow protection mechanism operative with time domain isolation  
A wireless communication device reduces undesired audio underflow in a digital to analog receive path that employs time domain isolation. One or more buffers in the receive path receive processed...
7412618 Combined alignment scrambler function for elastic interface  
An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state...
7412008 Programmable phase mapping and phase rotation modulator and method  
A modulator ( 10 ) and method provides a programmable phase rotation for supporting different modulation formats and different phase rotations. The modulator ( 10 ) includes a programmable symbol...
7406355 Method for generating playback sound, electronic device, and entertainment system for generating playback sound  
A method and electronic device for obtaining clear playback sound that is faithful to the original sound, in which data and audio data are played back under control of a CPU, and in accordance with...
7397882 Digital phase locked circuit capable of dealing with input clock signal provided in burst fashion  
A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if...
7394884 Synchronizing method  
To synchronize a regularly occurring pulse train to the average of a bunched pulse train, an oscillator generates a plurality of differently phase shifted signals at a given frequency. One of the...
RE40317 System for receiving a control signal from a device for selecting its associated clock signal for controlling the transferring of information via a buffer  
A computer system including a first component operated in response to the timing of a first clock, apparatus for storing information, apparatus for transferring information from the first component...
7369637 Adaptive sampling rate converter  
Apparatus, methods and techniques for adjusting the phase offset used in sampling rate conversion uses a Farrow structure or the like to compensate for clock problems such as “clock jitter”...
7366270 PLL/DLL dual loop data synchronization utilizing a granular FIFO fill level indicator  
A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. In particular, a system and method for dual loop data synchronization using a granular FIFO fill...
7352836 System and method of cross-clock domain rate matching  
Described are a system and method for providing an interface to synchronize data transfers across clock domains. A first pulse converter receives a request signal in a first clock domain and...
7349482 Echo canceller of ADSL system and training method thereof  
An echo cancellation circuit includes delay units at its input unit and output unit in order to adjust the delay caused by a FIFO. The delay times of the delay units are trained using a training...
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