Matches 151 - 200 out of 384 < 1 2 3 4 5 6 7 8 >
Match Document Document Title
6681272 Elastic store circuit with static phase offset  
An elastic store circuit using a first in/first out buffer (FIFO) to accurately control the phase delay in a waveform using the write (WR) and read (RD) clocks is provided. The FIFO reads the input...
6658074 Method and apparatus for reproducing clock signal of low order group signal  
In a clock signal reproducing circuit in a pulse stuffed synchronizing system, a destuffing circuit removes stuff pulses and unnecessary bits from a higher order group signal to output a lower...
6643345 Synchronous control apparatus and method  
A digital variable-frequency oscillator has an output frequency thereof variable in dependence upon a frequency control variable. Externally input data are stored in a data storage device, from...
6625241 Data communications bit stream combiner/decombiner  
A method and apparatus for multiplexing and demultiplexing multiple serial data streams provide double the data throughput on a single media channel, such as Fibre Channel (EC). A first incoming...
6603831 Synchronous digital data transmitter  
A data transmitter is having a source of data. The data is transmitted in response to clock pulses provided by a clock pulse generator. A buffer having a fixed data storage capacity is provided for...
6603817 Buffer circuit capable of correctly transferring small amplitude signal in synchronization with high speed clock signal  
Complementary signals on a pair of first signal lines are transferred onto a pair of second signal lines in synchronization with a clock signal by a buffer circuit. The buffer circuit includes an...
6597707 Circuitry, architecture and methods for synchronizing data  
An apparatus comprising a first programmable circuit configured to present (i) a first parallel data signal and (ii) a first control signal in response to one or more serial data signals and a...
6594329 Elastic buffer  
An NGIO Elastic Buffer is provided for enabling link data received from an NGIO link to be synchronized into a receiver clock domain of a data receiver responsible for processing that data in a...
6587530 Method and apparatus for signal integrity verification  
The present invention provides a signal integrity measurement method and apparatus which allows for signal characteristics to be measured by obtaining samples taken at the midpoint of the data...
6577693 Desynchronizer for a synchronous digital communications system  
A desynchonizer for a synchronous digital communications system serves to recover a useful signal from a synchronous digital input signal. It comprises a buffer for temporarily storing the input...
6570907 Simplified finite impulse response (FIR) digital filter for direct sequencespread spectrum communication  
A spread spectrum modulated signal generator is disclosed that reduces the storage requirement for storing values representing filter responses of input signal samples in a digital filter by taking...
6556560 Low-latency audio interface for packet telephony  
In a method for reducing latency in packet telephony caused by buffering at the conversion stage between analog audio signals and digital audio data, analog audio is sampled at a rate far greater...
6542564 Method and apparatus for compensating reproduced audio signals of an optical disc  
An apparatus and method for compensating audio signals to be recorded on an optical disc to optimize usage of memory in an audio decoding circuit, and to neutralize invalid audio data to produce...
6535567 Method and apparatus for suppression of jitter in data transmission systems  
A jitter suppression apparatus in a data transmission system includes a phase detector circuit to determine a plurality of phase errors between sync pulses of a data line and sync pulses of a...
6526069 Synchronization device for a synchronous digital message transmission system and process for producing a synchronous output signal  
A synchronization device for a synchronous digital message transmission system producing a synchronous output signal including successive transport modules synchronized to a frame clock from a...
6526108 Method for buffering the jitter processing of vocoder  
A method for processing received voice data in a voice data processing system including a receiving buffer. The method comprising steps of generating an interruption for processing the received...
6526110 Embedded RAM based digital signal processor  
An apparatus receives and demodulates digital signals encoded in multiple formats. The apparatus includes multiple processor units and a memory embedded with the processor units, and a cache...
6512804 Apparatus and method for multiple serial data synchronization using channel-lock FIFO buffers optimized for jitter  
The invention provides an apparatus, and related method, for receiving and synchronizing parallel data transmitted over multiple serial data channels. The synchronization technique uses a channel...
6507629 Address generator, interleave unit, deinterleave unit, and transmission unit  
An address generator for generating addresses in an prescribed order in the case of writing/reading data to/from predetermined storage means, comprises a first address data generating means for...
6501812 Method for reading and demodulating data at different rates  
A digital signal processing circuit having a memory for storing a digital signal obtained from a playback channel; a controller for writing the digital signal in the memory at a first rate and...
6501809 Producing smoothed clock and data signals from gapped clock and data signals  
A clock smoothing circuit generates a smoothed clock signal from a gapped clock signal having unevenly spaced pulses separated by gaps that result from the removal of data bits and from a reference...
6490329 Device and method for generating clock signals from a single reference frequency signal and for synchronizing data signals with a generated clock  
An integrated circuit device including a FIFO and a clock generator having a pulse swallower. The pulse swallower eliminates pulses from a reference frequency signal, producing a primary digital...
6463111 Method and apparatus for desynchronizing a DS-3 signal and/or an E3 signal from the data portion of an STS-STM payload  
The desynchronizer of the present invention includes two FIFOs. The first FIFO has two address counters (write and read), an intermediate count register, circuitry for calculating the difference...
6456678 Elastic store for wireless communication systems  
A system and method of buffering data of a wireless communication system. The system and method maintain synchronization, end-to-end signaling and coding overhead bits needed to encapsulate data...
6417705 Output driver with DLL control of output driver strength  
An output driver includes an adjustable main output stage and a control circuit with a digital delay locked loop (digital DLL) circuit and an adjustable scaled output stage. The main output stage...
6418176 Forwarded clock recovery with variable latency  
A technique provides data from an information signal. The technique involves receiving the information signal in the forwarded clock device synchronously with a forwarded clock signal. The...
6415006 Reducing waiting time jitter  
Circuits and methods are described which reduce waiting time jitter at a synchronizer/multiplexer by using a “sub-bit” comparison of a clock associated with an unsynchronized data stream and a...
6400785 Signal resynchronization apparatus having capability to avoid data corruption  
An apparatus for resynchronizing data signals by using dual port data buffer storage, which prevents data corruption and subsequent system disruption from happening by employing a mechanism to keep...
6400683 Adaptive clock recovery in asynchronous transfer mode networks  
In a data communication network, a system clock rate can be inferred at a receiver by measuring the data rate during successive periods. This information is used to adjust or adapt a receiver...
6389553 Redundant link delay maintenance circuit and method  
A system and method for maintaining a constant delay when a switch between two or more possible input data streams is made. Data received on a selected stream is buffered as it is received, the...
6377645 Method and apparatus for controlling bit slippage in high-speed communications systems  
A method and apparatus for controlling bit slips in a high-speed, two-way, communications channel. More particularly, the entire communications system, comprising, inter alia, a receiver, a...
6363132 Asynchronous data conversion system for enabling error to be prevented  
An asynchronous data conversion system enables high conversion efficiency and reliability to be secured because it is capable of preventing lack of the data or redundancy of the data, and if lack...
6356611 Bit rate control interface for the recording and/or reading of digital data  
A control interface for the bit rate of digital data to be recorded as well as a control interface for the bit rate of digital data emanating from a reading device, particularly when the digital...
6332072 Method and apparatus for detecting failures in a communication device BV signal metrics  
A communication device (101) includes multiple antennas (201-203), multiple receivers (222-224), and a processor (225). The communication device receives a first radio frequency (RF) signal via a...
6324235 Asynchronous sample rate tracker  
An asynchronous sample rate tracker based on a phase-locked loop quickly locks to an input sample rate, even when the input sample rate equals the resident, or internal, sample rate of an...
6314485 Automatic status register  
One aspect of the present invention provides a packer-unpacker (PUP) for a digital serial interface which allows a plurality of processors to access time slot registers of a serial data stream...
6298073 Method using elastic buffering for equalizing transmission delays in a non-earth-synchronous multiple satellite data transmission system  
A method for fixing the propagation delay between a user terminal and another station in a non-synchronous LEO satellite communications system, to adjust plural signals to have substantially...
6289066 Method and apparatus for recentering an elasticity FIFO when receiving 1000BASE-X traffic using minimal information  
A method and apparatus is provided that solves the problem of data overrun and underrun, for example in a system that exchanges data using the Gigabit Ethernet protocol. A single 8-bit data path is...
6289065 FIFO status indicator  
The invention relates to data transfers between devices having asynchronous clocks. A FIFO having multiple levels holds the data while en route from a sender to a receiver. The invention monitors...
6266381 Frequency control arrangement  
In a frequency control arrangement 200 of the type comprising an oscillator 270, a mark or space counter 210, a frequency detector 220 and an error signal calculator 230-260, 290 and in which it is...
6263036 Asynchronous signal input apparatus and sampling frequency conversion apparatus  
An asynchronous signal input apparatus includes a memory device which writes data that are input at a predetermined frequency, in response to a write signal, and reads data in response to a read...
6259727 Process and device for generating a plurality of derived clock signals  
A method and arrangements for extracting a plurality of clock signals for signal-processing circuits, in particular for a digital modem, from a supplied clock signal, for the clock signals to be...
6252919 Re-synchronization of independently-clocked audio streams by fading-in with a fractional sample over multiple periods for sample-rate conversion  
A net sample is added or removed from an audio sample stream by fading in or out fractional samples over many sample periods. A sample-rate converter has a FIFO that is written with an input sample...
6240106 Retiming arrangement for SDH data transmission system  
A retiming arrangement for use in a demultiplexer in an SDH data transmission system uses Bit Justification data, and not Pointer data, to modify a recovered clock signal and generate a clock...
6240195 Hearing aid with different assemblies for picking up further processing and adjusting an audio signal to the hearing ability of a hearing impaired person  
A hearing aid with different assemblies for picking up, further processing and adjusting an acoustic signal to the hearing ability of a hearing impaired person, wherein a digital signal processing...
6236695 Output buffer with timing feedback  
An output buffer circuit includes an adjustable delay time and is coupled to a reference output buffer which includes an adjustable delay time and a fixed delay time. In one embodiment, a...
6226338 Multiple channel data communication buffer with single transmit and receive memories  
A multiple-channel data communication buffer includes a transmit first-in-first-out ("FIFO") circuit and a receive FIFO circuit. The transmit and receive FIFO circuits each include a write pointer...
6219396 Jitter resistant clock regenerator  
A jitter resistant clock regenerator for receiving program data transmitted on a transmission channel in synchronism with a transmission clock signal and cancelling jitter, having occurred on the...
6215833 Digital signal processing circuit  
A digital signal processing circuit comprising a memory means for storing a digital signal obtained from a playback channel; a control means for writing the digital signal in the memory means at a...
6208703 First-in-first-out synchronizer  
A one stage first-in-first-out synchronizer includes a producer side and a consumer side. The producer side includes a first write buffer, a not full output, a write input, a second write buffer...
Matches 151 - 200 out of 384 < 1 2 3 4 5 6 7 8 >