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7349482 |
Echo canceller of ADSL system and training method thereof
An echo cancellation circuit includes delay units at its input unit and output unit in order to adjust the delay caused by a FIFO. The delay times of the delay units are trained using a training...
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7333581 |
Method of processing data for a decoding operation using windows of data
The present invention relates to a method using windows of data, a window (w) comprising data to be written and to be read and having a size. It is characterized in that it comprises:* A step of...
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7324620 |
Techniques to reduce transmitted jitter
A re-timer system that may include a phase recoverer (“PR”), first-in-first-out device (“FIFO”) and retime clock multiplication unit (“CMU”). PR may receive an input signal that suffers...
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7315539 |
Method for handling data between a clock and data recovery circuit and a data processing unit of a telecommunications network node of an asynchronous network, as well as a bit rate adaptation circuit and a clock and data recovery system
A method for handling data between a clock and data recovery system CDR and a data processing unit DP of a telecommunications network node TNN of an asynchronous communications network, using a bit...
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7315600 |
Asynchronous FIFO apparatus and method for passing data between a first clock domain and a second clock domain and a second clock domain of a data processing apparatus
An asynchronous FIFO apparatus includes a main FIFO memory, operable to store the data to be passed between the first and second clock domains, accessible from each clock domain under the control...
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7310396 |
Asynchronous FIFO buffer for synchronizing data transfers between clock domains
An asynchronous FIFO buffer communicates data between first and second clock domains. The FIFO buffer includes a shift register that accepts and shifts out data at a relatively high output...
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7305058 |
Multi-standard clock rate matching circuitry
Clock rate matching circuitry is provided to buffer data between two clock domains that may have slightly different frequencies. To facilitate supporting a wide range of different communication...
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7305059 |
Method and device for the clocked output of asynchronously received digital signals
A method and device for the uniform output of asynchronously transmitted digital values is provided, including: receiving the digital values in a receiver from a transmission path; outputting the...
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7298808 |
Cascaded jitter frequency shifting Δ-Σ modulated signal synchronization mapper
The invention provides a synchronizer incorporating a Δ-Σ modulator (i.e. a bit stuffing command generator), coupled in series with a frequency offset measurement block and a frequency-locked...
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7295641 |
Phase alignment circuitry and methods
The phase of a data signal relative to a reference clock signal is approximated relatively accurately using only relatively coarse increments of phase shift between trial version of a sampling...
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7269397 |
Method and apparatus for measuring communications link quality
A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A...
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7254207 |
Method and apparatus for transmitting and recieving multiplex tributary signals
A method and apparatus are provided for transmitting and receiving a plurality of individual tributary signals in multiplex form via a common line. At the transmitting end, the tributary signals,...
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7248661 |
Data transfer between phase independent clock domains
An integrated circuit arrangement clocked by a single clock having variable delays to different regions of said arrangement such that said regions are partially synchronized to each other, the...
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7248663 |
Apparatus and method for transforming data transmission speed
Disclosed is an apparatus and method for transforming data transmission speed that transforms data transmission speeds of data transmitting apparatuses that have different data transmission speeds...
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7245686 |
Fast skew detector
Signal processing apparatus, including a circuit which processes signals received on multiple channels so as to extract therefrom at least first and second sequences of symbols, and a FIFO, which...
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7242737 |
System and method for data phase realignment
A system and method for aligning data transferred across circuit boundaries having different clock domains. The system includes a buffer circuit comprising a latch for receiving data clocked in a...
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7242736 |
Data transfer
A receiver for digital data is provided. The receiver comprises a ring buffer operable to store received data. The receiver also comprises a write pointer controller for the buffer, operable to...
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7227876 |
FIFO buffer depth estimation for asynchronous gapped payloads
A desired FIFO buffer fill level is continuously derived during mapping or demapping of plesiosynchronous data signals into synchronized data signals, or vice-versa. One of j predefined integer...
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7227870 |
Systems including packet interfaces, switches, and packet DMA circuits for splitting and merging packet streams
An integrated circuit includes receive circuits for receiving packets, transmit circuits for transmitting packets, a packet DMA circuit for communicating packets to and from a memory controller,...
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7227484 |
Startup apparatus and technique for a wireless system that uses time domain isolation
A technique includes providing a butter to receive data from a processor of a wireless device in response to an active mode of the processor and selectively coupling an input terminal of a filter...
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7212599 |
Jitter and wander reduction apparatus
The present invention is for an apparatus that receives input data at a non-uniform first data rate carried by a system clock, and provides output data at a substantially uniform second data rate...
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7200197 |
Semiconductor integrated circuit
A semiconductor integrated circuit includes first and second data paths, first to third flip flops and logic circuits. The first data path transfers input data. The first flip flop is coupled to...
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7197100 |
High-speed interconnection adapter having automated lane de-skew
An adapter that buffers received symbols and automatically determines and corrects for skew between lanes is disclosed. In one embodiment, the adapter is a part of a network that includes a first...
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7194056 |
Determining phase relationships using digital phase values
Disclosed herein are circuits in which a plurality of clock signals are generated by corresponding clock generators from one or more common clock references. The clock generators accept control...
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7187741 |
Clock domain crossing FIFO
A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links...
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7184508 |
Capturing data and crossing clock domains in the absence of a free-running source clock
Data, such as data received by a memory I/O from a memory unit in a DDR SDRAM system, is captured using a trigger signal, which may be a non free-running clock signal such as a DQS signal in a DDR...
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7180914 |
Efficient asynchronous stuffing insertion and destuffing removal circuit
A digital communications system that can asynchronously map/de-map digital signals from one clock domain to another, while reducing mapping jitter levels and permitting higher levels of...
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7161999 |
Synchronizing data or signal transfer across clocked logic domains
A synchronization interface transfers multi-bit digital data or signal between multiple clocked logic domains while maintaining data or signal integrity. When deployed in a processor-based system,...
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7158599 |
Elastic store circuit
An elastic store circuit includes a set/reset flip-flop circuit corresponding to plural pieces of input data and an AND circuit for receiving the output of each flip-flop circuit. Upon receipt of a...
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7154977 |
Techniques to reduce transmitted jitter
A re-timer system that may include a phase recoverer (“PR”), first-in-first-out device (“FIFO”) and retime clock multiplication unit (“CMU”). PR may receive an input signal that suffers...
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7154419 |
Audio apparatus for processing voice and audio signals
An audio apparatus for performing digital data processing on voice and audio signals through interrelated data sampling and processing. A predetermined mixing processing in the audio apparatus is...
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7145974 |
Apparatus and method for transmitting data between transmission systems using dissimilar phase clocks
An apparatus and a method for transmitting data between transmission systems using clock sources having dissimilar phases is disclosed. After monitoring a state of a transmission system of the...
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7133654 |
Method and apparatus for measuring communications link quality
A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A...
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7120171 |
Packet data processing apparatus and packet data processing method
In real time communication, long interruption of a media data signal caused by underflow or overflow of a buffer is reduced. A monitoring unit 35 a monitors a state of the buffer 34 periodically....
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7120215 |
Apparatus and method for on-chip jitter measurement
A jitter measurement circuit is described comprising delay elements arranged in a serially-connected chain, and first and second sets of circuitry. Each delay elements has an associated delay, an...
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7110422 |
Method and apparatus for managing voice call quality over packet networks
The present invention relates to an apparatus and method for maintaining voice call quality over a packet network by providing optimal de-jitter buffer depth and rate of change of depth. Buffer...
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7103128 |
Data synchronization circuit and communication interface circuit
There is provided a data synchronization circuit for synchronizing a (n+1) (n: natural number) bit bus data synchronous with a first clock with a second clock, comprising: a first circuit for...
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7103129 |
System and method for rate adaptation in a wireless communication system
A wireless telephone includes first and second baseband processors. The first baseband processor functions as system master, and the second processor functions as system slave. The first baseband...
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7099426 |
Flexible channel bonding and clock correction operations on a multi-block data path
An elastic buffer for buffering a stream of data blocks includes a controller and a memory space, wherein multiple data blocks can be written and read during a single write or read clock cycle,...
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7099416 |
Single ended termination of clock for dual link DVI receiver
A receiver includes clock termination circuitry that is capable of applying either a terminating impedance or a high impedance to a transmission path that carries a clock signal. When multiple of...
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7099425 |
Adjustment circuit and method for tuning of a clock signal
An integrated circuit and a method for tuning an internal clock signal with respect to data that is to be emitted includes an adjustment circuit with a compensating circuit for synchronizing the...
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7092473 |
Method for the selection (puncturing) of data bits
A method for the selection (puncturing) of data bits from a data word in a data processing system, notably a communication system, wherein, within one cycle of operation of a working processor, the...
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7076016 |
Method and apparatus for buffering data samples in a software based ADSL modem
A method and apparatus for buffering data samples in a software-based ADSL modem. The method includes receiving samples of data in a buffer and determining if the received samples of data will...
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7065132 |
Memory-free retimer
A method of transmitting digital signals which are passed via a communication system by means of a retimer between an input and an output, whereby according to the invention the data packet applied...
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7054400 |
Digital AV signal processing apparatus
A digital AV signal processing apparatus includes a buffer for storing digital data input to the digital AV signal processing apparatus, and outputting the digital data as output digital data, a...
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7042932 |
Synchronization detection architecture for serial data communication
A method includes receiving an indication of incoming data from a first serial bus and buffering the bits to accommodate a difference between a first rate of the incoming data and a second rate of...
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7039145 |
Control loop apparatus and method therefor
In the field of optical communications, the need to remove jitter from a Synchronous Digital Hierarchy (SDH) or Synchronous Optical NETwork (SONET) datastream is recognized. Consequently, the...
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7039144 |
Large-input-delay variation tolerant (LIDVT) receiver adopting FIFO mechanism
The present invention discloses a multiple-stage FIFO mechanism capable of receiving data signals correctly. The circuit includes a write-enable pulse sequencer for sequentially generating a...
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7027547 |
Method and apparatus for matching transmission rates across a single channel
The invention provides a novel scheme to match the clock rates along a single transmission channel. The rate matching aspect of this invention receives a character stream synchronized by a first...
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7023942 |
Method and apparatus for digital data synchronization
Synchronization and desynchronization of a data signal transported in a synchronous frame across a synchronous communications network, such as SONET/SDH, reduces waiting-time jitter. A timing...
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