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7620857 |
Controllable delay device
Two delay chains having in each case n series-connected unidirectional delay elements are provided for controllably delaying electrical signals between a circuit input and at least one circuit...
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7620136 |
Clock and data recovery circuit having gain control
A clock and data recovery circuit includes a phase detector configured to compare a phase of a data signal to a phase of a sampling clock to provide a phase error signal, a gain stage configured to...
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7620133 |
Method and apparatus for a digital-to-phase converter
A DPC ( 300 ) includes: a frequency source ( 310 ) for generating a clock signal; a delay line ( 320 ) for receiving the clock signal and generating phase-shifted clock signals at output taps; a...
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7619547 |
Serial-to-parallel converter circuit and liquid crystal display driving circuit
A serial-to-parallel converter circuit comprising: an m-bit serial data holding unit to be input with serial data whose input bit number is set to m or n (<m) bits within a transfer period and a...
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7616725 |
Signal delay structure in high speed bit stream demultiplexer
A signal delay structure and method of reducing skew between clock and data signals in a high-speed serial communications interface includes making a global adjustment to the clock signal in the...
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7616721 |
Apparatus and method for checking network synchronization clock signal in communication system
In an apparatus and method for checking a network synchronization clock signal in a communication system, the apparatus generates a divided clock signal which is the same as an externally inputted...
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7613266 |
Binary controlled phase selector with output duty cycle correction
A phase selection circuit having a selection circuit, binary weighted current sources, and an amplifier circuit. The phase selection circuit is configured for selecting adjacent phase signals from...
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7610161 |
Wander gamut display
A wander gamut display for perturbation analysis is created by determining from a periodic input data signal and a reference clock a frequency offset and frequency drift rate for the input signal....
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7609798 |
Calibrating a phase detector and analog-to-digital converter offset and gain
The present invention includes apparatus and methods to calibrate a phase detector and an analog-to-digital converter (ADC) offset and gain. In one such embodiment, an apparatus includes a phase...
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7609796 |
Communication control apparatus and a method for freely controlling the transmission of time slots
A communication control apparatus includes a signal receiver for receiving a state variable signal indicating a timing of data transmission from a neighboring node. The apparatus also includes a...
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7609102 |
Pattern-dependent phase detector for clock recovery
A phase detector apparatus and method used for clock recovery from a data signal is provided. The phase detector provides phase correction signals to a clock signal generator, where the phase...
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7606343 |
Phase-locked-loop with reduced clock jitter
The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a...
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7606342 |
Tracking the phase of a received signal
The tracking of the phase of a received signal having a known preamble is accomplished by the steps of: initializing a phase-locked loop in accordance with estimated phase parameters, which are...
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7606341 |
Circuit for bit alignment in high speed multichannel data transmission
An alignment circuit is configured to receive a reference clock signal (ref_clk) derived from a main clock having a period T and successive sets of 2n data bits that are transmitted in parallel on...
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7606340 |
Phase detection device and method thereof
A phase detection device comprising an analog-digital converter, an interpolator, and a determining unit. The analog-digital converter receives an analog signal and converts the analog signal to a...
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7602874 |
Providing accurate time-based counters for scaling operating frequencies of microprocessors
A mechanism provides accurate time-based counters for scaling operating frequencies of microprocessors. The mechanism makes use of a time-based counter circuit configuration in which a fixed...
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7602873 |
Correcting time synchronization inaccuracy caused by asymmetric delay on a communication link
Techniques for correcting time synchronization inaccuracy caused by asymmetric delays on a communication link. Time synchronization according to the present techniques includes determining an...
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7602859 |
Calibrating integrating receivers for source synchronous protocol
An embodiment of the present invention is a technique to calibrate an integrating receiver. A delay calibration circuit calibrates an adjusting code of a chain of delay elements and positioning of...
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7602852 |
Initial parameter estimation in OFDM systems
A coarse estimate of a location of an information carrying part of a symbol in a received signal in a telecommunication system is generated. This involves generating correlation values by...
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7599461 |
Method and apparatus for generating one or more clock signals for a decision-feedback equalizer using DFE detected data in the presence of an adverse pattern
Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data, in the presence of an adverse pattern, such as a Nyquist...
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7599458 |
System and method to reduce jitter
One disclosed embodiment may comprise an interpolation system that includes an interpolator that interpolates between a selected phase from a preceding cycle and a selected phase from a current...
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7596173 |
Test apparatus, clock generator and electronic device
There is provided a clock generator for generating a single-phase clock into which jitter has been injected, having a multi-phase clock generating section for generating a plurality of clock...
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7593498 |
Method and apparatus for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications
Methods and apparatus are provided for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications. An interface is provided for use...
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7593470 |
High-speed communication system with a feedback synchronization loop
In a communications device having a physical layer device and a processing device connected to the physical layer device, the number of input/output (I/O) ports required for communication between...
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7590212 |
System and method for adjusting the phase of a frequency-locked clock
A clock signal regeneration system and method to adjust the phase of a frequency-locked clock signal is provided. The system includes a numerically controlled oscillator, a clock source, and an...
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7590170 |
Method and apparatus for measuring jitter
A system and method for characterizing the jitter of a periodic signal. Samples of the signal are taken with a sampling device. A set of samples representing a particular value of the signal in...
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7587015 |
Asynchronous digital data capture
The present invention provides asynchronous digital capture by first, capturing the digital output of the device under test (DUT) clock on an automated test equipment (ATE) digital channel. Next,...
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7587012 |
Dual loop clock recovery circuit
A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference...
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7583774 |
Clock synchroniser
A clock synchronizer, for generating a local clock signal synchronized to a received clock signal, is described and claimed, along with a corresponding clock synchronization method. The clock...
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7583772 |
System for shifting data bits multiple times per clock cycle
A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following...
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7583770 |
Multiplex signal error correction method and device
A method of reducing a phase error caused by a plurality of error sources in a signal in the form of a sequence of a plurality of digital partial signals associated with a number of subcarriers (k)...
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7580495 |
Mixer-based phase control
A phase control circuit includes a signal generator sub-circuit that generates a set of phase reference signals having phase angles generally distributed over a phase angle adjustment range. A...
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7580493 |
Electronic circuit
One embodiment of a method of generating a clock signal and synchronizing the generated clock signal with a digital data stream comprises generating a clock signal using an oscillator, identifying...
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7580491 |
Quarter-rate clock recovery circuit and clock recovering method using the same
A quarter-rate clock recovery circuit includes a clock generator, a phase interpolation unit, a phase detector, and a controller. The clock generator generates first through fourth clocks having a...
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7580477 |
Transmission system enabling reliable reception by a single device of information in channels concurrently transmitted on different frequencies
This device utilizes frames transported on carriers of different frequencies (BCCH ext CBCH(SD/8)). For processing the information coming from these frames, the device comprises a transceiver...
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7579867 |
Restructuring data from a trace buffer of a configurable IC
Some embodiments provide a method that outputs from a configurable IC a first set of data bits from a trace buffer. Each bit of the first set of data bits is simultaneously generated in the...
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7577226 |
Clock recovery circuitry
Clock recovery circuitry for recovering a clock signal from a data signal is disclosed. The clock recovery circuitry comprises sampling unit ( 46 ) for sampling the data signal at a plurality of...
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7577225 |
Digital phase-looked loop
Embodiments of the invention include an integrated circuit including a phase-locked loop (PLL). The integrated circuit includes a phase detector, a frequency detector, a loop filter, a...
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7577224 |
Reducing phase offsets in a phase detector
In one embodiment, the present invention includes a system having an amplifier to receive an incoming signal and a recovery circuit coupled to the amplifier that includes a phase detector to adjust...
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7577221 |
Receiver scheme for synchronous digital transmission
A method, apparatus and system for improving the tolerance for timing jitter noise by eliminating the need to recover clock information from the input signal. There is no need to communicate clock...
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7573968 |
Data transmission circuit with serial interface and method for transmitting serial data
A data transmission circuit includes a first clock generating circuit that generates a first clock; a second clock generating circuit that generates a second clock, which is different from the...
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7573967 |
Input threshold adjustment in a synchronous data sampling circuit
A data sampler system receives a high-speed data stream and uses a first set of data samplers for sampling the data stream at a first set of clock phase angles to produce a first set of sequential...
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7571363 |
Parametric measurement of high-speed I/O systems
A phase comparator is used to test a device under test comprising an input/output (I/O) circuit by applying a signal to the device under test; extracting a phase signal from the phase comparator;...
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7571338 |
Determining a time difference between first and second clock domains
Buffer circuitry receives data to be processed by electronic circuitry using a first clock signal associated with a first clock domain. The buffered data is output using a second clock signal...
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7570727 |
Data transmission controller and sampling frequency converter
In a data transmission controller apparatus, a first-in first-out storage stores newly inputted data in response to a write request signal, and reads and outputs the stored data which has been...
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7570726 |
Master device with time domains for slave devices in synchronous memory system
A method of operating a master/slave system includes the step of identifying a master receive data phase value to coordinate the transfer of data from a slave device without phase alignment...
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7570725 |
Numerically controlled oscillator
A numerically controlled oscillator (NCO) is arranged to accumulate control values for each transition of a system clock to provide an accumulation signal and an edge signal. A speed multiplier...
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7570721 |
Apparatus and method for multi-phase digital sampling
A method and apparatus for determining a relationship between an input signal frequency and a reference signal frequency is envisioned. The system derives a plurality of internal reference signals...
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7570684 |
Method for joint time synchronization and frequency offset estimation in OFDM system and apparatus of the same
Embodiments of the present invention include a method for performing joint time synchronization and carrier frequency offset estimation in a wireless communication system, comprising steps of: on a...
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7570659 |
Multi-lane receiver de-skewing
A technique for de-skewing a group of serial data signals respectively outputted from a group of data lanes includes simultaneously feeding a test signal to inputs of the group of data lanes and...
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