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9036763 Methods and devices for implementing all-digital phase locked loop  
An all-digital phase locked loop includes a time to digital converter that determines a fractional portion of a phase count. The time to digital converter has a quantization error that may be...
9036756 Receiver and methods for calibration thereof  
There is disclosed a receiver and associated methods in which a received signal can be sampled at the symbol rate rather than oversampled. This reduction in the sampling frequency compared with...
9036740 Performing image rejection on bandpass signals  
An image rejection (IR) circuit is configured to receive a complex signal from a radio frequency (RF) mixer, where the complex signal includes an in-phase signal portion and a quadrature signal...
9025716 Inter-integrated circuit-slave interface, and method for operating an inter-integrated circuit-slave interface  
An I2C interface is provided which has a data line and a clock line, the clock line having a first input buffer, and the data line having a second input buffer and an output buffer, the data line...
9025650 Multiple receivers in an OFDM/OFDMA communication system  
A signal receiver is configured to receive multiple time-domain input signals. A plurality of the input signals among the multiple time-domain input signals is selected and transformed into...
9018990 Duty cycle tuning circuit and method thereof  
A duty cycle tuning circuit and a method thereof are provided, in which the duty cycle tuning circuit includes multiple interpolation circuits, an edge detection circuit, and a delay chain. Each...
9014321 Clock drift compensation interpolator adjusting buffer read and write clocks  
In at least some embodiments, an electronic device includes a data sink and a buffer coupled to the data sink. The buffer is configured to receive streaming data in transit to the data sink. The...
9014250 Filter for impulse response shortening with additional spectral constraints for multicarrier transmission  
A channel in a multiple carrier communication system is equalized by computing a desired spectral response, shortening the impulse response of the channel so that a significant part of an energy...
9014322 Low power and compact area digital integrator for a digital phase detector  
In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for...
9008165 Digital phase equalizer for serial link receiver and method thereof  
An apparatus of automatic power control for burst mode laser transmitter and method are provided. In one implementation a method includes: pushing a first multi-bit data into a data memory;...
9008252 Circuit, method and mobile communication device  
A circuit includes an oscillator, a variable phase adjuster and a feedback loop. The oscillator is configured to provide an RF signal, wherein the oscillator is configured to operate in a...
9001275 Method and system for improving audio fidelity in an HDMI system  
HDMI is a digital audio and video communications protocol commonly used in consumer electronics. HDMI is particularly synonymous with high fidelity audio and video. Even though HDMI is a digital...
9001952 Master slave interface  
Implementations related to systems, devices, and methods that make use of a master slave arrangement are described. In one implementation, a method of reducing overall power consumption in a...
9001949 Methods and QAM receiver for performing timing recovery  
A method in a QAM receiver (100) for performing timing recovery. The QAM receiver (100) is configured to receive a sequence of symbols. Each symbol is represented by a respective IQ pair...
9001951 Techniques for transferring time information between clock domains  
A circuit includes a logic circuit, first and second storage circuits, a timing detection circuit, and a compensation circuit. The logic circuit generates a digital value in response to a first...
9001953 Phase interpolation circuit and receiver circuit  
A phase interpolation circuit includes: a first circuit configured to generate a first intermediate signal by weighting first reference signals having different phases with a first ratio and...
8995598 Low jitter clock recovery circuit  
A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase...
8995599 Techniques for generating fractional periodic signals  
A phase-locked loop circuit includes phase detection circuitry to generate a first control signal based on a phase comparison between first and second periodic signals. An oscillator circuit...
8995597 Digital second-order CDR circuits  
A method for performing a clock and data recovery includes providing data and a clock; determining early/late values of the data to generate a first-order phase code using the data and the clock;...
8994425 Techniques for aligning and reducing skew in serial data signals  
A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first...
8990605 Apparatus and method for read preamble disable  
A memory device is provided. The memory device includes a preamble disable memory and a memory controller. The preamble disable memory is arranged to store preamble disable data. The preamble...
8989328 Systems and methods for serial communication  
This disclosure includes a point-to-point two-lineserial interface (TSI) suitable for use in a wireless communications device as well as in other applications. The TSI may employ a protocol...
8989324 Receiver and receiving method  
Embodiments of the present invention provide a receiver and a receiving method. The receiver comprises: a branch forming unit a plurality of signal branches; each of the signal branches comprising...
8989329 Eye width measurement and margining in communication systems  
Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver...
8989137 Signal generation method and signal generation device  
A transmission method simultaneously transmitting a first modulated signal and a second modulated signal at a common frequency performs precoding on both signals using a fixed precoding matrix and...
8982938 Distortion measurement for limiting jitter in PAM transmitters  
Methods and test equipment for measuring jitter in a Pulse Amplitude Modulated (PAM) transmitter. Under one procedure, a first two-level PAM signal test pattern is used to measure clock-related...
8982974 OFDM clock recovery  
Receiver synchronization techniques (RST), contributing more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of...
8982999 Jitter tolerant receiver  
An embodiment of the invention includes a receiver with reduced error terms and incoming jitter tracking that improves jitter tolerance. An embodiment provides these benefits based on a voltage...
8976054 Time-to-digital conversion circuit and time-to-digital converter including the same  
A time-to-digital conversion circuit for converting a time difference between two input signals to a 1-bit digital value, and adjusting the time difference between the two input signals to...
8971468 Increasing the resolution of serial data recovery units (DRUs) based on interleaved free running oversamplers  
The methods and apparatus disclosed herein provide an operative system for increasing the resolution of serial DRUs based on interleaved free running oversamplers. In particular, this system uses...
8971469 Serial data communication method and serial data communication device  
A master device and slave devices are connected with each other through an SDA and an SCL, and at least one of a serial communication data signal communicated through the SDA and a serial...
8970420 Bipolar time-to-digital converter  
Representative implementations of devices and techniques provide bipolar time-to-digital conversion. For example, either a positive time duration or a negative time duration may be converted to a...
8964924 Method and device for clock recovery  
A method and a device for processing a signal determine a timing phase over an observation interval of an input signal. A frequency estimation is determined based on the timing phase. A phase...
8964925 Multi-rate control loop for a digital phase locked loop  
Methods and systems to generate control signals for timing recovery of a signal received over baseband communications systems are disclosed. The timing control circuit uses a multi-rate DSP...
8964923 Low latency high bandwidth CDR architecture  
Provided is a low latency high bandwidth clock and data recovery (CDR) system. For example, there is a low latency high bandwidth CDR system including a demultiplexer configured to convert a high...
8964919 System and method for determining a time for safely sampling a signal of a clock domain  
A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a phase estimate of a first clock domain is calculated based on a...
8964922 Adaptive frequency synthesis for a serial data interface  
Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally....
8958516 NICAM decoder with output resampler  
A NICAM audio signal re-sampler may include a non-linear interpolator configured to interpolate in a non-linear manner between sequential digital samples that are based on a stream of demodulated...
8958491 Receiving device of OFDM communication system and method for alleviating phase noise thereof  
The present invention relates to a receiving apparatus in an OFDM communication system and a phase noise mitigation method thereof which are configured to estimate and compensate for phase noise...
8958515 SerDes jitter tolerance BIST in production loopback testing with enhanced spread spectrum clock generation circuit  
A system for controllably generating jitter in a serial data stream includes a frequency generator and first and second mixers. The frequency generator is configured to output in-phase and...
8958517 Clock phase adjustment for a low-latency FIFO  
In a clock-adjustment circuit, a phase-detection circuit receives a first clock associated with a first clock domain and a second clock associated with a second clock domain, and determines a...
8948331 Systems, circuits and methods for filtering signals to compensate for channel effects  
Embodiments of circuits and methods are described for decreasing transmitter waveform dispersion penalty (TWDP) in a transmitter. A data stream is received for transmission across a channel and a...
8948330 Systems and methods for performing variable structure timing recovery  
In accordance with an embodiment of the disclosure, systems and methods are provided for aligning signals in a timing recovery system. In certain implementations, a coarse phase error indicative...
8942317 Carrier offset correction of a received signal  
Apparatuses, methods and systems for mitigating carrier offset of a received signal are disclosed. One embodiment of a receiver includes a receiver chain operative to receive a communication...
8942280 Method and apparatus for timing jitter measurement  
A timing jitter measurement circuit for measuring timing jitter in the digital domain may use an interpolator bank to over-sample a signal from a media reader, a zero crossing estimator to...
8942337 Systems and methods for handling race conditions during data transfer in an implantable medical device  
The accuracy of data processing operations in implantable medical devices is improved through reductions in errors associated with data acquisition, reading, and transmission. In one embodiment,...
8934524 Method for detecting with a high temporal accuracy a threshold crossing instant by a signal  
A method detects a threshold crossing instant at which a signal crosses a threshold, by: sampling the signal at plural sampling instants spaced from one another by a sampling period; detecting...
8934597 Multiple delay locked loop integration system and method  
A delay locked loop (DLL) circuit having an expanded operating frequency range is achieved by providing multiple DLLs, each having a different range of operating frequencies. A selection mechanism...
8934598 Integrated video equalizer and jitter cleaner  
An integrated system for adaptive equalization and jitter reduction of a video signal that includes an adaptive equalizer and a jitter cleaner located on one integrated circuit within a single...
8934592 Method for reducing data alignment delays  
A method is provided for synchronizing binary data transmitted in parallel via N channels. The method comprises performing at the receiver side, a data-clock-alignment for the data in the N...