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7616722 Method and circuitry for extracting clock in clock data recovery system  
A method for extracting a clock in a clock data recovery system is provided. The method includes the following steps. First, a serial link transmission data is sampled for a plurality of times, and...
7616721 Apparatus and method for checking network synchronization clock signal in communication system  
In an apparatus and method for checking a network synchronization clock signal in a communication system, the apparatus generates a divided clock signal which is the same as an externally inputted...
7616708 Clock recovery circuit  
A clock recovery circuit comprising an initial delay select circuit, a delay locked loop and a clock synthesizer circuit is provided. The initial delay select circuit comprises an initial timing...
7613265 Systems, methods and computer program products for high speed data transfer using an external clock signal  
Systems, methods and computer program products for capturing data. The methods include receiving an external clock signal having a first frequency, a first edge and a second edge. A clock period of...
7613264 Flexible sampling-rate encoder  
A method for implementing a flexible sampling-rate encoder, comprising the steps of (A) sampling an input signal at a regular time-interval to produce sampled data, (B) generating a pseudo-random...
7580493 Electronic circuit  
One embodiment of a method of generating a clock signal and synchronizing the generated clock signal with a digital data stream comprises generating a clock signal using an oscillator, identifying...
7574350 Passive data carrier with signal evaluation means for evaluating information of a self-clocking signal  
A data carrier ( 2 ) that is developed for contactless receiving of a signal, wherein the data carrier ( 2 ) can be supplied with energy and information by the signal, provides data carrier...
7570721 Apparatus and method for multi-phase digital sampling  
A method and apparatus for determining a relationship between an input signal frequency and a reference signal frequency is envisioned. The system derives a plurality of internal reference signals...
7567629 Multiphase clock recovery  
The invention represents a parallel and distributed approach to clock recovery based on multiple mutually phase shifted sample clock signals (åS) defining a set of orthogonal clock phases. The...
7567533 Packet detection system, packet detection device, and method for receiving packets  
A packet detector for a multi-band orthogonal frequency division multiplexing system includes a plurality of packet detection units each corresponding to a time frequency code for detecting packets...
7545848 High resolution time stamps for periodic samples  
A method and apparatus for collecting digital sample data from a target system accesses the digital sample data at transitions of a sample clock, acquires information related to an instantaneous...
7505541 NRZ/PAM-4/PRML triple mode phase and data detector  
The multi-mode phase and data detector includes a phase detector and a charge pump. A plurality of latching blocks clocked on complimentary phases of a feedback signal produces a plurality of phase...
7502434 Frequency detector including a variable delay filter  
A frequency detector and frequency-locked loop suitable for use in a clock recovery circuit are disclosed. The detector is linear, and can be used in implementing a loss of lock indicator. Variable...
7489754 Frequency-lock detector  
A frequency-lock detector (FLD) adapted to register more than one target count per period of a target clock signal to generate a count value related to a frequency difference between the target...
7477713 method for providing automatic adaptation to frequency offsets in high speed serial links  
Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the...
7466969 MIMO receiver, MIMO reception method and wireless communication system  
A MIMO receiver, a MIMO reception method and a wireless communication system capable of accurate MMSE control even when each transmit antenna uses a different chip power ratio in MIMO filter...
7466783 Method and system to implement a double data rate (DDR) interface  
Embodiments of the invention relate to a method and system to implement a DDR interface, such as a high-speed encode/decode interface. In one embodiment, a method of encoding data comprises the...
7453970 Clock signal selecting apparatus and method that guarantee continuity of output clock signal  
Provided are a clock signal selecting apparatus and method that can guarantee the continuity of an output clock signal. The clock signal selecting apparatus and method can synchronize the phases of...
7434084 Method and apparatus for eliminating sampling errors on a serial bus  
A synchronous bit-serial data interface utilizes a transmitter that transmits a data stream having duplicates of each data bit. The receiver samples the data stream utilizing either the rising or...
7424077 Jitter sensitive maximum-a-posteriori sequence detection  
A channel detector has an anchor points inserter, a desired signal calculator, a distance calculator and a data detector. The anchor points inserter is adapted to choose values of expected...
7424059 Data transfer circuit  
A transmission unit loads transmission data on a first register and outputs it to a transfer line and starts counting the transmission clock signals in a strobe generation counter according to a...
7424046 Spread spectrum clock signal generation system and method  
A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a...
7421029 Impulse response shortening and symbol synchronization in OFDM communication systems  
A method for receiving at a receiver having a variable filter a transmitted signal that includes a periodic training signal. The method includes (a) receiving and sampling the transmitted signal at...
7415089 High-speed serial link clock and data recovery  
A system for clock and data recovery (“CDR”) includes a clock generator, a half-rate phase detector for receiving the input data, an encoder, a phase selector outputting recovered clock, a...
7412016 Data-level clock recovery  
A circuit for adjusting the phase of a clock signal. A first sampling circuit generates a sequence of data samples in response to transitions of the clock signal, each of the data samples having...
7397876 Methods and arrangements for link power reduction  
Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data...
7382845 Distribution of synchronization in an ethernet local area network environment  
Systems and methods are described for distribution of synchronization in a packet switched local area network environment. A method for extracting network synchronization timing from a data...
7372931 Unit interval discovery for a bus receiver  
A bus data signal is applied to a tapped data delay line. The various increasingly delayed data values present at the taps of the delay line are clocked into respective cells of a sticky ZEROs...
7362837 Method and apparatus for clock deskew  
A clock signal is deskewed relative to a data signal by sweeping a sampling point in time and sweeping an amplitude offset. Bit error measurements are made at each sampling point in time and...
7359471 Data communication method and data communication device and semiconductor device  
The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data...
7356108 OFDM receiver having adaptive channel estimator for correcting channel fading based on accumulated pseudo power values  
A channel estimator is configured for determining a gain adjustment for a received wireless signal having a prescribed plurality of tones. The channel estimator is configured for generating, for...
7352771 Data collision detection device and method  
A data collision detection device that includes a means for de-modulating at least one carrier signal corresponding to a received modulated subcarrier signal from at least one data transmitter to...
7349510 Apparatus for data recovery in a synchronous chip-to-chip system  
An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling...
7349509 Multi rate clock data recovery based on multi sampling technique  
A clock and data recovery device (CDR) based on multi-rate multi-phase oversampling technique is capable of receiving serial data streams of different data rates. The CDR uses a multi-rate...
7342969 Signaling with multiple clocks  
At least two sequences of predetermined reference times are established on respective ones of at least two communication lines. At least some of the reference times of at least one of the sequences...
7321647 Clock extracting circuit and clock extracting method  
In a clock extracting circuit according to the present invention, after serial data is subjected to oversampling using a reference clock of 2N times a frequency of the serial data, clock timing in...
7321617 Data communication system with self-test feature  
A data communication system includes circuitry to assure components respond to variations in the time length of the valid data window or “eye” of the high speed data communication signal. A...
7317775 Switched deskew on arbitrary data  
A method and circuit capable of handling skew between a clock and data signal up to +/− one half bit on a random input data pattern. A digital algorithm cycles through each data bit and...
7317489 Teletext data detection by data content based synchronization and error reduction  
A technique to provide a cost effective solution to detect teletext data that can reduce detected error in teletext when the transmission data rate is known. In one example embodiment, this is...
7310400 Data recovery device and method  
A data recovery device. The device adjusts a digital signal according to a pulse signal output by a phase-locked loop circuit. The sampling circuit samples each bit of the digital signal five times...
7308048 System and method for selecting optimal data transition types for clock and data recovery  
A clock recovery circuit samples an incoming data stream that includes sequences of signal transitions. A transition detector categorizes the received signal transitions into various types, such as...
7284141 Method of and apparatus for measuring jitter and generating an eye diagram of a high speed data signal  
A sampling system is disclosed which measures high speed data signals by performing sampling events at intervals determined by a programmable DDS output frequency and a programmable counter. The...
7257173 Bounding box signal detector  
A description of signal behavior in the vicinity of a time and voltage of interest is produced by defining a region in the (time, voltage) plane that is a closed straight sided figure whose...
7242735 Data recovery system and the method thereof  
A data recovery system and method is disclosed, which comprises an oversampler, a phase detection circuit, a data pick circuit, a data overlap/skip detection circuit and a data correction circuit....
7239813 Bit synchronization circuit and central terminal for PON systems  
A bit synchronization circuit composed of a multiphase data sampling unit for converting each received burst data sets to multiphase data trains, a phase determination unit for generating a control...
7236555 Method and apparatus for measuring jitter  
In a method for measuring jitter, a signal under test is inputted to generate signal transition locations. A signal transition location is latched using a sampling clock signal, and the signal...
7221725 Host interface data receiver  
A host interface includes transition detection circuitry, transition phase averaging circuitry, and bit stream sampling circuitry. The transition detection circuitry receives an incoming bit stream...
7212580 Multi-level signal clock recovery technique  
Clock recovery of a multi-level (ML) signal can be performed in a two-step process. First, the transitions within the ML signal can be detected by a novel transition detector (TD). And second, the...
7151811 Electric circuit for decoding a two-phase asynchronous data signal and corresponding decoding method, device for controlling equipment  
This invention relates to an electronic circuit for decoding an asynchronous two-phase data signal. According to the invention, such an electronic circuit comprises means for generating a decoding...
7149268 Digital subscriber line driver  
A digital subscriber line (DSL) driver allows a transmitter to monitor its own transmit spectrum at the subscriber loop and adjust the transmit spectrum based on detected line conditions, affected...
Matches 1 - 50 out of 249 1 2 3 4 5 >