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7630730 Apparatus and method for time control of the processing of a radio signal in a mobile station  
The apparatus contains a counter that is synchronized to the reference time in the mobile station. The counter counts sampled chips of the radio signal to produce a count. The apparatus further...
7627068 Apparatus for frequency synchronization and method for the same  
An apparatus and method for frequency synchronization is proposed to obtain the pilot tones and evaluate the frequency offset and time offset for frequency synchronization. The frequency...
7627071 Timing synchronization module and method for synchronously playing a media signal  
The timing synchronization module includes a phase locked loop (PLL) and a synchronization processing unit. The PLL receives an output-end clock signal. When the PLL receives the output-end clock...
7616721 Apparatus and method for checking network synchronization clock signal in communication system  
In an apparatus and method for checking a network synchronization clock signal in a communication system, the apparatus generates a divided clock signal which is the same as an externally inputted...
7609751 Method and apparatus to initiate communications between an unknown node and an existing secure network  
A first node initiating communications with a second node already in a secure network sends a discovery burst having a preamble portion and a payload portion. The preamble portion is sent at a...
7599457 Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits  
In one embodiment of the invention, a clock-and-data-recovery (CDR) system has a multi-phase clock generator that generates a plurality of phase-offset clock signals and one or more channel...
7587015 Asynchronous digital data capture  
The present invention provides asynchronous digital capture by first, capturing the digital output of the device under test (DUT) clock on an automated test equipment (ATE) digital channel. Next,...
7573932 Spread spectrum clock generator  
A spread spectrum clock generator includes a non-volatile memory to store control codes corresponding to a predetermined delay. A delay circuit receives a control code having a predetermined number...
7567533 Packet detection system, packet detection device, and method for receiving packets  
A packet detector for a multi-band orthogonal frequency division multiplexing system includes a plurality of packet detection units each corresponding to a time frequency code for detecting packets...
7561582 Data reception device  
A data reception device having a reception data buffer unit storing a plurality of packets contained in a data packet, a reception data amount measuring unit measuring the data amount stored in the...
7555087 Clock data recovery circuitry with dynamic support for changing data rates and a dynamically adjustable PPM detector  
Clock data recovery (CDR) circuitry can be provided with dynamic support for changing data rates caused by the interfacing of different protocols. The CDR circuitry, which operates in reference...
7542536 Resampler for a bit pump and method of resampling a signal associated therewith  
A resampler, method of resampling a signal and a bit pump and transceiver employing the same. In one embodiment, the resampler includes an interpolation stage, coupled to an input of the resampler,...
7526023 Programmable cross-talk cancellation in programmable logic device  
Circuitry is provided in a programmable logic device incorporating clock-data recovery circuitry on I/O channels to allow the use of otherwise unused noise-reduction circuits in the I/O channels,...
7515665 GFSK/GMSK detector with enhanced performance in co-channel interference and AWGN channels  
A detector for detecting a received signal according to a Gaussian shift keying (“GFSK/GMSK”) modulation scheme. The detector may enhance a detection performance of the receiver while limiting...
7515614 Source synchronous link with clock recovery and bit skew alignment  
A high speed transmission system transfers data streams over a set of data links. Each data link may carry a number of bit streams. A clock signal is not transmitted over the optical link. Instead,...
7512158 Jitter prevention in a digital communication network  
A server apparatus receives packetized data and transmits the packetized data over a network. The apparatus includes an input for receiving the packetized data from a signal source. An AC clock...
7477712 Adaptable data path for synchronous data transfer between clock domains  
Systems and methods for implanting synchronous data transfer between clock domains are disclosed. An exemplary system may comprise an adaptable data path having an input for receiving a signal from...
7450530 Cross link multiplexer bus configured to reduce cross-talk  
A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The plurality of cross link multiplexers has a destination port configured to...
7450529 Cross link multiplexer bus  
A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The plurality of cross link multiplexers has a destination port configured to...
7436918 Output stage synchronization  
Systems and methods for transferring data across clock domains in a manner that avoids metastability of the data and is very tolerant of variations in the clock signals of the different clock...
7424078 Synchronous compensator adaptively defining an enable range for synchronous compensation  
In the synchronous compensator, a load generator loads a bit counter with data in dependence upon whether or not a detection signal from a UW detector falls within the range indicated by an enable...
7424046 Spread spectrum clock signal generation system and method  
A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a...
7409020 Technique for filter-enhanced clock synchronization  
A technique for filter-enhanced clock synchronization is disclosed. In one particular exemplary embodiment, the technique may be realized by/as a method for filter-enhanced clock synchronization....
7398411 Self-calibrating time code generator  
Provided is a self-calibrating time code generator and method for generating an accurate time code (e.g., an accurate IRIG waveform). The self-calibrating time code generator includes a...
7382845 Distribution of synchronization in an ethernet local area network environment  
Systems and methods are described for distribution of synchronization in a packet switched local area network environment. A method for extracting network synchronization timing from a data...
7366267 Clock data recovery with double edge clocking based phase detector and serializer/deserializer  
A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols....
7342953 Synchronization detection circuit  
A synchronization detection circuit includes: a matched filter 105 for outputting a correlation value, between a spreading code and data that is obtained by sampling a code spread signal 101 ,...
7317489 Teletext data detection by data content based synchronization and error reduction  
A technique to provide a cost effective solution to detect teletext data that can reduce detected error in teletext when the transmission data rate is known. In one example embodiment, this is...
7298800 Analog signal control method, analog signal controller, and automatic gain controller  
An analog signal control method for accurately controlling an analog signal irrespective of a latency. The analog signal control method includes the steps of converting the analog signal to a...
7275174 Self-aligning data path converter for multiple clock systems  
A system and method for aligning an input signal ( 24 ) synchronized to a first clock signal ( 22 ) with a second clock signal ( 26 ) The invention includes a mechanism ( 106 ) for generating a...
7274230 System and method for clockless data recovery  
A system for clockless synchronous data recovery is provided. The system includes an input rate demultiplexer receiving a serial data stream of bits of data transmitted at a bit rate and generating...
7272202 Communication system and method for generating slave clocks and sample clocks at the source and destination ports of a synchronous network using the network frame rate  
A communication system, source and destination ports of the communication system, and methodology is provided for transporting data in one of possibly three different ways. Data is transported...
7263150 Probability estimating apparatus and method for peak-to-peak clock skews  
A probability estimating apparatus and method for peak-to-peak clock skews for testing the clock skews among a plurality of clock signals distributed by a clock distributing circuit, and for...
7260164 Efficient filtering of RxLOS signal in SerDes applications  
An efficient filter circuit and method for filtering a loss of receiver signal prevents false signals caused by glitches. The short glitches that happen at the positive edge of the clock signal may...
7245684 System and method for compensating for skew between a first clock signal and a second clock signal  
A system and method for compensating for skew in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry...
7245683 System and methods of recovering a clock from NRZ data  
A substantially passive implementation of a clock recovery circuit may be employed to reduce or eliminate the amount of jitter added to the recovered clock by the recovery circuitry. NRZ data may...
7242734 Frame boundary discriminator  
A frame boundary discriminator has a first input for receiving a high speed master clock signal having a multitude of master clock pulses within a frame, and a second input for receiving...
7239813 Bit synchronization circuit and central terminal for PON systems  
A bit synchronization circuit composed of a multiphase data sampling unit for converting each received burst data sets to multiphase data trains, a phase determination unit for generating a control...
7230956 Techniques for frame detection and word alignment  
A system receives input data frames that are configured according to a SONET or an SDH standard. The input data is converted to parallel data. The system provides groups of bits along parallel...
7209530 Multi-shelf system clock synchronization  
A method and apparatus for conveying to a control shelf of a multi-shelf network node any master clock signal received via a plurality of interface cards associated with a plurality of peripheral...
7203809 Data transfer control method, and peripheral circuit, data processor and processing system for the method  
A memory 1 performs its internal operation in response to access requests ( 200, 201 and 202 ) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 ...
7190709 Early-late correlation for timing error correction in data communication receivers  
A timing error correction technique for use in data communications receivers such as WLAN (Wireless Local Area Network) receivers is provided where an input signal is received that has a timing...
7154946 Equalizer and equalization method for return-to-zero signals  
An equalizer for return-to-zero (RZ) signals comprises: (a) an equalizer core for equalizing the received signal; (b) a decision corrector for detecting and correcting misplaced pulses and double...
7120814 System and method for aligning signals in multiple clock systems  
A system and method for aligning an input signal ( 24 ) synchronized to a first clock signal ( 22 ) with a second clock signal ( 26 ). The invention includes a mechanism ( 106 ) for generating a...
7100067 Data transmission error reduction via automatic data sampling timing adjustment  
A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and...
7095818 Data transmission process with auto-synchronized correcting code, auto-synchronized coder and decoder, corresponding transmitter and receiver  
A data transmission process with auto-synchronised correcting code, auto-synchronised coder and decoder, corresponding transmitter and receiver. According to the invention, synchronisation...
7082142 System and method for delivering content in a unicast/multicast manner  
The present invention is a system and method for enabling multicast synchronization of initially unicasted content. Multiple unicast streams are synchronized in order to convert the unicast streams...
7076012 Measure-controlled delay circuit with reduced playback error  
A timing control circuit for synchronizing an output clock signal with an input clock signal includes a pulse generator, a measure delay array, a measure circuit, and a forward delay array. The...
7068746 Base station transceiver to radio network controller synchronization filtering function  
A method for synchronizing communications in a wireless communications network wherein time synchronization is performed between a clock master and a clock slave. To achieve synchronization between...
7062003 Self-tuning baud rate generator for UART applications  
The invention describes a baud rate generator for use in a sampled data system. This generator makes possible the sampling of asynchronous digital input data when its baud rate is not known, and...
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