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7424078 Synchronous compensator adaptively defining an enable range for synchronous compensation  
In the synchronous compensator, a load generator loads a bit counter with data in dependence upon whether or not a detection signal from a UW detector falls within the range indicated by an enable...
7424046 Spread spectrum clock signal generation system and method  
A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a...
7409020 Technique for filter-enhanced clock synchronization  
A technique for filter-enhanced clock synchronization is disclosed. In one particular exemplary embodiment, the technique may be realized by/as a method for filter-enhanced clock synchronization....
7398411 Self-calibrating time code generator  
Provided is a self-calibrating time code generator and method for generating an accurate time code (e.g., an accurate IRIG waveform). The self-calibrating time code generator includes a...
7382845 Distribution of synchronization in an ethernet local area network environment  
Systems and methods are described for distribution of synchronization in a packet switched local area network environment. A method for extracting network synchronization timing from a data...
7366267 Clock data recovery with double edge clocking based phase detector and serializer/deserializer  
A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols....
7352835 Clock data recovery circuitry with dynamic support for changing data rates and a dynamically adjustable PPM detector  
Clock data recovery (CDR) circuitry can be provided with dynamic support for changing data rates caused by the interfacing of different protocols. The CDR circuitry, which operates in reference...
7342953 Synchronization detection circuit  
A synchronization detection circuit includes: a matched filter 105 for outputting a correlation value, between a spreading code and data that is obtained by sampling a code spread signal 101 ,...
7317489 Teletext data detection by data content based synchronization and error reduction  
A technique to provide a cost effective solution to detect teletext data that can reduce detected error in teletext when the transmission data rate is known. In one example embodiment, this is...
7298800 Analog signal control method, analog signal controller, and automatic gain controller  
An analog signal control method for accurately controlling an analog signal irrespective of a latency. The analog signal control method includes the steps of converting the analog signal to a...
7275174 Self-aligning data path converter for multiple clock systems  
A system and method for aligning an input signal ( 24 ) synchronized to a first clock signal ( 22 ) with a second clock signal ( 26 ) The invention includes a mechanism ( 106 ) for generating a...
7274230 System and method for clockless data recovery  
A system for clockless synchronous data recovery is provided. The system includes an input rate demultiplexer receiving a serial data stream of bits of data transmitted at a bit rate and generating...
7272202 Communication system and method for generating slave clocks and sample clocks at the source and destination ports of a synchronous network using the network frame rate  
A communication system, source and destination ports of the communication system, and methodology is provided for transporting data in one of possibly three different ways. Data is transported...
7263150 Probability estimating apparatus and method for peak-to-peak clock skews  
A probability estimating apparatus and method for peak-to-peak clock skews for testing the clock skews among a plurality of clock signals distributed by a clock distributing circuit, and for...
7260164 Efficient filtering of RxLOS signal in SerDes applications  
An efficient filter circuit and method for filtering a loss of receiver signal prevents false signals caused by glitches. The short glitches that happen at the positive edge of the clock signal may...
7245684 System and method for compensating for skew between a first clock signal and a second clock signal  
A system and method for compensating for skew in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry...
7245683 System and methods of recovering a clock from NRZ data  
A substantially passive implementation of a clock recovery circuit may be employed to reduce or eliminate the amount of jitter added to the recovered clock by the recovery circuitry. NRZ data may...
7242734 Frame boundary discriminator  
A frame boundary discriminator has a first input for receiving a high speed master clock signal having a multitude of master clock pulses within a frame, and a second input for receiving...
7239813 Bit synchronization circuit and central terminal for PON systems  
A bit synchronization circuit composed of a multiphase data sampling unit for converting each received burst data sets to multiphase data trains, a phase determination unit for generating a control...
7230956 Techniques for frame detection and word alignment  
A system receives input data frames that are configured according to a SONET or an SDH standard. The input data is converted to parallel data. The system provides groups of bits along parallel...
7209530 Multi-shelf system clock synchronization  
A method and apparatus for conveying to a control shelf of a multi-shelf network node any master clock signal received via a plurality of interface cards associated with a plurality of peripheral...
7203809 Data transfer control method, and peripheral circuit, data processor and processing system for the method  
A memory 1 performs its internal operation in response to access requests ( 200, 201 and 202 ) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 ...
7190709 Early-late correlation for timing error correction in data communication receivers  
A timing error correction technique for use in data communications receivers such as WLAN (Wireless Local Area Network) receivers is provided where an input signal is received that has a timing...
7177380 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
System and methods of recovering a clock from NRZ data  
A substantially passive implementation of a clock recovery circuit may be employed to reduce or eliminate the amount of jitter added to the recovered clock by the recovery circuitry. NRZ data may...
7154946 Equalizer and equalization method for return-to-zero signals  
An equalizer for return-to-zero (RZ) signals comprises: (a) an equalizer core for equalizing the received signal; (b) a decision corrector for detecting and correcting misplaced pulses and double...
7120814 System and method for aligning signals in multiple clock systems  
A system and method for aligning an input signal ( 24 ) synchronized to a first clock signal ( 22 ) with a second clock signal ( 26 ). The invention includes a mechanism ( 106 ) for generating a...
7100067 Data transmission error reduction via automatic data sampling timing adjustment  
A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and...
7095818 Data transmission process with auto-synchronized correcting code, auto-synchronized coder and decoder, corresponding transmitter and receiver  
A data transmission process with auto-synchronised correcting code, auto-synchronised coder and decoder, corresponding transmitter and receiver. According to the invention, synchronisation...
7082142 System and method for delivering content in a unicast/multicast manner  
The present invention is a system and method for enabling multicast synchronization of initially unicasted content. Multiple unicast streams are synchronized in order to convert the unicast streams...
7076012 Measure-controlled delay circuit with reduced playback error  
A timing control circuit for synchronizing an output clock signal with an input clock signal includes a pulse generator, a measure delay array, a measure circuit, and a forward delay array. The...
7068746 Base station transceiver to radio network controller synchronization filtering function  
A method for synchronizing communications in a wireless communications network wherein time synchronization is performed between a clock master and a clock slave. To achieve synchronization between...
7062003 Self-tuning baud rate generator for UART applications  
The invention describes a baud rate generator for use in a sampled data system. This generator makes possible the sampling of asynchronous digital input data when its baud rate is not known, and...
7061939 Source synchronous link with clock recovery and bit skew alignment  
A high speed transmission system transfers data streams over a plurality of data links. Each data link may carry a number of bit streams. On the transmitting end, multiplexers serialize the bit...
7042971 Delay-locked loop with built-in self-test of phase margin  
A method and apparatus for measuring phase margin of a delay-locked loop (DLL) is provided in which a reference clock is applied to a reference input of the DLL. An auxiliary variable delay is...
6990417 Jitter estimating apparatus and estimating method  
There is provided a jitter estimating apparatus for calculating phase noise waveform of an input signal and for estimating a peak value, a peak-to-peak value and a worst value of jitter of the...
6990162 Scalable clock distribution for multiple CRU on the same chip  
A scalable clock recovery system. In one embodiment the system comprises a clock master unit, a clock distribution network, and a plurality of clock recovery units. The master clock unit generates...
6990123 Method and apparatus for redundant transmission over TDMA optical networks  
Communication between a burst manager and plural remote terminals over a first passive optical network (PON) and a second PON, with each PON having a downstream portion and an upstream portion,...
6987824 Method and system for clock/data recovery for self-clocked high speed interconnects  
A method and system is provided for clock/data recovery for self-clocked high speed interconnects. A data signal is received and then equalized. The equalized data signal then provides the trigger...
6977966 Bidirectional optical communications having quick data recovery without first establishing timing and phase lock  
A method of transmitting and rapidly recovering a burst of data without first having to establish a timing or phase lock. The signals are transmitted as modified Manchester coded signals having...
6956918 Method for bi-directional data synchronization between different clock frequencies  
A method for bi-directional data synchronization between different clock frequencies is described wherein a state machine counter is provided a first clock signal having a first frequency. The...
6940934 Synchronizing signal processing circuit  
A synchronizing signal processing circuit for use in a video apparatus such as a display apparatus and an information recording/reproducing is disclosed. The synchronizing signal processing circuit...
6934348 Device for recovering burst-mode optical clock  
Disclosed is a device for recovering a burst-mode clock. The burst-mode clock recovery device includes a delay unit and a logic element. A reference clock is produced by implementing a logic...
6928126 Reception interface unit in transmission system  
A reception interface unit in a transmission system wherein time series data is divided into data groups and a data packet with reproduction specification time data specifying a time at which each...
6917658 Clock recovery method for bursty communications  
Clock recovery method for bursty communications. A method is disclosed for recovering the clock from a received data stream that comprising bursts of data with zones of substantially no data...
6911663 Transmission circuit and semiconductor device  
There is provided a transmission circuit which can certainly perform transmission of data of digital form between two circuits operating in synchronization with two clock signals having the same...
6891475 Low-power passive transponder  
The invention concerns a radio-frequency transponder ( 12 ) for contact-free identification with a reader ( 10 ), comprising: an antenna ( 24 ), an analog circuit ( 25 ) including a capacitor ( 32...
6879602 Synchronizing method and bridge  
An offset value corresponding to the difference between counter values of cycle time counters in two buses is obtained and stored, so that the buses are connected, the value of a first cycle time...
6868111 Methods and systems for identifying transmitted codewords after loss of synchronization in spread spectrum communication systems  
A method and system for maintaining synchronization and identifying received codewords in a spread spectrum communication system is disclosed. According to the method and system, a spread spectrum...
6801585 Multi-phase mixer  
A wireless receiver apparatus including a voltage controller oscillator and mixer. The voltage controlled oscillator generates a first signal having a first frequency, and a second signal having...
6795657 Circuit and method for monitoring optical signal level  
A circuit for monitoring an optical signal level provided in an optical receiver includes a clock extraction circuit, a noise detection circuit, and an alarm circuit. The clock extraction circuit...
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