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9042504 Communication channel calibration for drift conditions  
A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data...
9042503 Data recovery circuit and operation method thereof  
In a data recovery circuit, a sampling circuit is configured to sample data using a plurality of sampling clock signals having different phases relative to one another and to output a plurality of...
9042431 Wide band deterministic interface  
A transceiver with non-deterministic delay characteristics is analyzed and adjusted to provide a transceiver with deterministic delay characteristics. The transceiver may be implemented with a...
9036758 Method and apparatus for detecting envelope  
A method and apparatus for detecting an envelope are provided. The method and apparatus may detect an envelope of a modulating signal based on a low calculation complexity and a simple circuit...
9036764 Clock recovery circuit  
This disclosure provides a clock recovery circuit having a phase-locked loop (PLL) with two-point modulation. A binary phase-error signal controls a variable frequency oscillator's (VFO's)...
9036757 Post-cursor locking point adjustment for clock data recovery  
Embodiments include systems and methods for applying post-cursor locking point adjustment to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a...
9036999 Frame/symbol synchronization in coherent optical OFDM  
One aspect provides an optical communication system. The system includes an optical-to-digital converter, a frequency estimator and a symbol synchronizer. The optical-to-digital converter is...
9036756 Receiver and methods for calibration thereof  
There is disclosed a receiver and associated methods in which a received signal can be sampled at the symbol rate rather than oversampled. This reduction in the sampling frequency compared with...
9036754 Circuit for a radio system, use and method for operation  
A circuit and method of operation for a circuit of a radio system in which a system time is divided into symbols, in which a system clock generator is activated in an operating mode, so that the...
9036755 Circuits and methods for time-average frequency based clock data recovery  
A clock data recovery circuit includes a binary phase detector configured to receive an incoming data signal and a recovered clock, and output a phase offset signal and recovered data; a digital...
9031179 Calibration of clock path mismatches between data and error slicer  
Embodiments include systems and methods for calibrating effective clock path mismatches in a receiver circuit. For example, a serializer/deserializer (SERDES) circuit includes a data slicer that...
9025713 Method for portable device processing data based on clock extracted from data from host  
A method for a first electronic device processing data based on information from a second electronic device may comprise: receiving a first signal from the second electronic device; extracting a...
9020087 All digital burst-mode clock and data recovery (CDR)  
The present invention relates to a clock and data recovery (CDR) unit comprising of a bang-bang phase detector to receive data and a recovered clock from a phase selector multiplexer. The phase...
9020086 Clock data recovery circuit module and method for generating data recovery clock  
A clock data recovery circuit module including a clock recovery circuit, a frequency comparison circuit and a signal detecting circuit is provided. The clock recovery circuit is configured to...
9020085 Method and apparatus for sampling point optimization  
A method and apparatus for timing optimization are disclosed, which rely on information gathered from a timing detection circuit to find the optimal sampling point of a data recovery system. In an...
9021137 Massively scalable object storage system  
Several different embodiments of a massively scalable object storage system are described. The object storage system is particularly useful for storage in a cloud computing installation whereby...
9014307 Radio to analog-to-digital sample rate decoupled from digital subsystem  
A multichannel radio receiver may include a radio frequency (RF) subsystem and a digital subsystem. The RF subsystem may be configured to provide analog information associated with a radio band to...
9008196 Updating interface settings for an interface  
A computer system includes a processor, and the processor includes at least one interface for communicating with an electronic component. Each of the at least one interface has a set of interface...
9001275 Method and system for improving audio fidelity in an HDMI system  
HDMI is a digital audio and video communications protocol commonly used in consumer electronics. HDMI is particularly synonymous with high fidelity audio and video. Even though HDMI is a digital...
9001949 Methods and QAM receiver for performing timing recovery  
A method in a QAM receiver (100) for performing timing recovery. The QAM receiver (100) is configured to receive a sequence of symbols. Each symbol is represented by a respective IQ pair...
8994571 Compact high-speed analog-to-digital converter for both I and Q analog to digital conversion  
An analog-to-digital converter (ADC) and a receiver that includes the ADC is disclosed. The ADC includes a first filter configured to receive a signal in an I-signal path of the receiver and a...
8994565 Analog to digital conversion apparatus with a reduced number of ADCs  
An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected...
8989321 Preamble detection based on repeated preamble codes  
Systems, methods, and other embodiments associated with preamble detection based on repeated preamble codes are described. According to one embodiment, an apparatus is provided that wirelessly...
8989246 Method and circuit of clock and data recovery with built in jitter tolerance test  
A clock and data recovery circuit with built in jitter tolerance test is disclosed. Imposing jitter on a filter inside a CDR loop to cause phase disturbances to the clock and data recovery...
8989328 Systems and methods for serial communication  
This disclosure includes a point-to-point two-lineserial interface (TSI) suitable for use in a wireless communications device as well as in other applications. The TSI may employ a protocol...
8989329 Eye width measurement and margining in communication systems  
Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver...
8983013 Signal processing circuit and signal processing method  
A signal processing circuit includes: a delay line configured to output, to a plurality of taps, signals with different delay times obtained by delaying an input signal, respectively; and a...
8983014 Receiver circuit and semiconductor integrated circuit  
In a receiver circuit which can correct a deviation of phase between an input signal and a clock, a sampler detects an amplitude level of the input signal at timing indicated by the clock, a first...
8983012 Receive timing manager  
A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data...
8982998 Transmission and reception apparatus and method  
A transmission apparatus includes a plurality of orthogonal frequency division multiplexing (OFDM) modulation signal generators, which generate a first OFDM modulation signal and a second OFDM...
8971468 Increasing the resolution of serial data recovery units (DRUs) based on interleaved free running oversamplers  
The methods and apparatus disclosed herein provide an operative system for increasing the resolution of serial DRUs based on interleaved free running oversamplers. In particular, this system uses...
8971447 Variable delay of data signals  
A data signal delay system may include a delay unit and a phase interpolation unit. The delay unit may include multiple delay elements that each have an element delay. The delay unit may be...
8971424 Combining pilot-symbol-based phase estimation with data-symbol-based phase estimation  
A method for a receiver to estimate phase of a carrier wave, including receiving a carrier wave carrying pilot symbols and data symbols extending between the pilot symbols, determining phase of...
8964921 Information processing apparatus, method, and program  
The present invention relates to an information processing apparatus, a method, and a program capable of suppressing deterioration of content quality. An integrated reception buffer time...
8964920 Auto-determining sampling frequency method and device thereof  
The present disclosure provides an auto-determining sampling frequency method. The method is for determining sampling frequency for an input signal of a single wire transmission interface. Each...
8964919 System and method for determining a time for safely sampling a signal of a clock domain  
A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a phase estimate of a first clock domain is calculated based on a...
8964922 Adaptive frequency synthesis for a serial data interface  
Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally....
8957793 Limit equalizer output based timing loop  
Aspects of the disclosure provide a method. The method includes boosting a portion of frequency components of a digital signal that is converted from an analog signal based on a clock signal,...
8958513 Clock and data recovery with infinite pull-in range  
A device and method for clock and data recovery are disclosed. For example, an integrated circuit comprises a first branch for recovering a clock signal from an input signal. The first branch...
8958469 Digital receiver equalization system  
A digital receiver equalization system has a digitized signal input derived from an analog front-end of a digital receiver and having a relatively wide bandwidth. A synthesis channelizer...
8953729 Method for symbol sampling in a high time delay spread interference environment  
Symbol sampling in a high time delay spread interference environment includes acquiring (602) a time varying baseband waveform. The waveform has a signal amplitude that varies between one of a...
8953668 Method and circuit of clock and data recovery with built in jitter tolerance test  
A clock and data recovery circuit with built in jitter tolerance test is disclosed. Imposing jitter on a filter inside a CDR loop to cause phase disturbances to the clock and data recovery...
8948320 Frame and symbol timing recovery for unbursted packetized transmissions using constant-amplitude continuous-phase frequency-modulation  
A system and method for performing frame and symbol timing synchronization on samples of a received signal that includes a series of frames. Each frame includes a known preamble and payload data....
8948314 Symbol timing recovery with multi-core processor  
A method of performing timing error detection includes receiving, by a multi-core processor, a data stream and up-sampling the data stream by a plurality of processing cores of the multi-core...
8948329 Apparatus and methods for timing recovery in a wireless transceiver  
Apparatus and methods for use in a wireless communication system are disclosed for recovery of timing tracking in a device, such as a wireless transceiver, after decoding errors occur due to...
8942334 Parallel replica CDR to correct offset and gain in a baud rate sampling phase detector  
Apparatus and methods reduce channel-dependent phase detector offset and/or gain errors. A conventional Mueller-Muller phase detector places a main cursor at the midpoint of a pre-cursor and a...
8942280 Method and apparatus for timing jitter measurement  
A timing jitter measurement circuit for measuring timing jitter in the digital domain may use an interpolator bank to over-sample a signal from a media reader, a zero crossing estimator to...
8942312 WCDMA modulation  
This disclosure describes techniques for modulating data. In one embodiment, these techniques include receiving an I or Q value, generating a time-shifted sample of a shaped pulse based on the I...
8938014 System and method for side band communication in SERDES transmission/receive channels  
A serializer/deserializer for a network device includes a data module configured to generate parallel data and side band data. A serializer is configured to convert the parallel data to serialized...
8934593 Very high precision device for measuring the time a signal is input  
The invention provides a device including a binary pulse input signal converter, the output of which is connected to a counter and to a delay line that includes a plurality of delay elements. The...