Matches 401 - 450 out of 971 < 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 >
Match Document Document Title
7006577 Apparatus and method for detecting transmission mode in digital audio receiver using null symbols  
An apparatus and method for detecting a transmission mode in digital audio receivers using the null symbol length which varies depending on the transmission mode. The transmission mode is...
7003016 Maximum likelihood timing synchronizers for sampled PSK burst TDMA system  
A method of producing a correction signal includes receiving a predetermined data sequence ( 500 ). The data sequence is sampled at predetermined times, thereby producing a sampled data sequence (...
7003027 Efficient PCM modem  
Apparatus and devices used to achieve a computationally efficient modem having a transmit path and a receive path. The apparatuses include a Farrow phase shifter for shifting the phase of signals...
6999543 Clock data recovery deserializer with programmable SYNC detect logic  
In a CDR (clock data recovery) deserializer, a clock divider receives a recovered clock signal (SCLK) and generates a divided clock signal (RPCLK). The frequency of the divided clock signal is...
6996202 Multiple channel adaptive data recovery system  
A microprocessor controlled data recovery unit with an adjustable sampling and signal comparison level. The data recovery unit includes a data channel and a monitor channel. The monitor channel...
6996200 Device for use in controlling a sample rate  
A first device comprises a loop circuit to control a sample rate of a digital circuit element. A circuit comprises a digital loop circuit to control a sample rate of a digital circuit element to be...
6996201 Data receiving system robust against jitter of clock  
A plurality of delay circuits successively delay a received data. The received data and delayed data signals are sampled in response to both leading and trailing edges of a clock having a frequency...
6996162 Correlation using only selected chip position samples in a wireless communication system  
A method ( 70 ) of operating a wireless receiver (UST). The method receives a wireless communicated signal, wherein the signal comprises a first synchronization channel component. The method also...
6996193 Timing error detection circuit, demodulation circuit and methods thereof  
A timing error detection circuit capable of detecting a timing error of symbols in a signal with a simple and small-sized configuration, comprising a sampling circuit for sampling a signal...
6993104 Apparatus and method for adaptively adjusting a timing loop  
A method and apparatus for adaptively adjusting the parameters of a timing loop based upon frequency errors between a data signal and a receiver's clock that is being used to sample the data signal...
6990161 Phase selection mechanism for optimal sampling of source synchronous clocking interface data  
Phase selection mechanisms for the optimal sampling of data at the receiving end of a SSC interface. The receiver is allowed to choose between several phases of its local clock, to best synchronize...
6990160 Reception apparatus and method  
A phase of a sampling clock provided from clock generating circuit 107 is switched periodically and alternately with a phase difference of 180 degrees, and during a period of each phase, timing...
6990061 Method and apparatus for channel estimation  
This invention relates to a method and apparatus for channel estimation. A method of determining a maximum likelihood frequency domain estimate of the channel response of a channel between at least...
6987410 Clock recovery circuit and communication device  
A clock recovery circuit includes plural stages of first variable delay elements for sequentially delaying a data signal by a first delay amount, plural stages of second variable delay elements for...
6988216 Method and system for synchronizing data  
A method and system that synchronizes time-related data in a digital processing system. The data to be synchronized includes display data such as audio or video data and command data such as...
6985549 Blind cost criterion timing recovery  
Symbol timing recovery employs a blind cost criterion from the Bussgang class of functions, and its stochastic gradient, to generate a timing phase error used to adjust sampling of received...
6985548 System and method for timing recovery in a discrete multi-tone system  
A system and method for performing pilot tone based timing recovery in a communication system using the discrete multi-tone (DMT) modulation. In DMT modulation, interference is introduced to the...
6982575 Clock ratio data synchronizer  
A clock ratio data synchronizer is provided that utilizes a plurality of flip flops to synchronize data received by the synchronizer from first clock domain logic at a first clock frequency to a...
6975673 Narrow-band interference rejecting spread spectrum radio system and method  
A spread spectrum receiver and method having narrow-band interference rejection of narrow-band jamming signals using digital signal processing frequency domain techniques. The method performed in...
6973147 Techniques to adjust a signal sampling point  
Techniques to adjust sampling times of an input signal. The techniques may utilize multi-level modification of the phase of a sampling clock. For example, the level of modification of the phase of...
6973142 Timing synchronization for M-DPSK channels  
The present invention discloses an improved method of timing synchronization with transmitted data packets in a receiver on a communication channel using differential phase shift keying (DPSK)...
6967694 Demodulator for demodulating digital broadcast signals  
To present a digital broadcast demodulator, in a demodulator of digital terrestrial wave broadcast for transmitting coded digital video and audio information in a packet form, capable of detecting...
6968024 Apparatus and method for operating a master-slave system with a clock signal and a separate phase signal  
A master-slave system includes a clock and phase signal generator to produce a clock signal at a given frequency and a phase signal at an effective frequency, where the phase signal may or may not...
6968025 High-speed transmission system having a low latency  
In addition to a first transmitter circuit, a plurality of transmission lines and a first data processing circuit in the receive side, so as to cause a DLL circuit to be regulated that regulates...
6961863 Techniques for facilitating conversion between asynchronous and synchronous domains  
An interface for use between an asynchronous domain and a synchronous domain is described. The asynchronous domain is characterized by transmission of data in accordance with a delay-insensitive...
6961861 Globally clocked interfaces having reduced data path length  
A interface, which connects memory and an integrated circuit, having a write path and read path that allow synchronous data propagation is provided. Further, a method for synchronizing data...
6959058 Data recovery apparatus and method for minimizing errors due to clock skew  
A data recovery apparatus for minimizing errors due to clock skew and a data recovery apparatus therefor are provided. The data recovery apparatus comprises a phase locked loop (PLL), an...
6956919 Single clock data communication in direct stream digital system  
Methods and apparatus are provided for receiving DSD data in phase modulation mode using a single clock signal. Either the bit clock or phase signal may be used.
6956918 Method for bi-directional data synchronization between different clock frequencies  
A method for bi-directional data synchronization between different clock frequencies is described wherein a state machine counter is provided a first clock signal having a first frequency. The...
6954506 Clock signal recovery circuit used in receiver of universal serial bus and method of recovering clock signal  
A clock signal recovery circuit that is implemented in a receiver of a universal serial bus (USB) and a method for recovering a clock signal. The clock signal recovery circuit comprises a phase...
6952399 Method and apparatus for synchronizing the coding and decoding of information in an integrated services hub  
A method and system for extrapolating a sampling rate from received digital cells in an integrated services hub in residential or business telecommunication systems. The system is implemented by a...
6952461 Sampling frequency conversion apparatus  
A sampling frequency conversion apparatus which easily controls the phase difference (time difference) between the input data and the output data in converting the sampling frequency, includes a...
6950484 Linearized digital phase-locked loop method  
A method for synchronizing a clock signal to a data signal, comprising the steps of (A) detecting an edge of the data signal, (B) determining whether a position of the edge is within a zone and (B)...
6950485 Precision timing generator apparatus and associated methods  
A precision timing generator includes a combiner that provides a timing signal by combining a coarse timing signal and a fine timing signal derived from a phase-shifted sinusoidal signal that has a...
6950475 OFDM receiver clock synchronization system  
A method is disclosed for synchronizing a OFDM signal. The method includes receiving an OFDM signal including a plurality of long and short synchronization symbols, each comprising a plurality of...
6946886 Clock-synchronized serial communication device and semiconductor integrated circuit device  
In a clock-synchronized serial communication device, a counter counts pulses in a communication clock signal. When the count reaches 8, the counter sets a start signal. With this start signal, a...
6944251 Digital phase lock loop circuit  
The digital phase locked loop circuit according to the invention includes a GAC circuit ( 4 ) for calculating the average frequency of the phase locked sampling clock signals in selected channels...
6940936 Alternate timing signal for a vestigial sideband modulator  
A remodulator timing signal ( 35 ) is generated by a phase locked loop ( 33 ) which is coupled to a broadcast vestigial sideband signal ( 5 ). Within the signal ( 5 ) is highly accurate timing data...
6941484 Synthesis of a synchronization clock  
A method, system, and device capable of generating one or more clocks internally to detect, sample, and receive synchronous data streams and eliminate the need for corresponding external...
6937679 Spread spectrum clocking tolerant receivers  
In some embodiments, the invention includes a system having a clock recovery circuitry to receive a data signal and a reference clock signal and in response thereto to produce an in phase clock...
6931085 Process and apparatus for correction of a resampler  
An apparatus for correction of a resampler is provided, with which a sampled input signal, that is subjected to an input sampling rate and which has a chip frequency that differs from the input...
6931562 System and method for transferring data from a higher frequency clock domain to a lower frequency clock domain  
A system and method for transferring data from circuitry disposed in a higher frequency clock domain actuated by a first clock signal to circuitry disposed in a lower frequency clock domain...
6928574 System and method for transferring data from a lower frequency clock domain to a higher frequency clock domain  
A system and method for transferring data from circuitry disposed in a lower frequency clock domain actuated by a first clock signal to circuitry disposed in a higher frequency clock domain...
6928570 System clock synchronization circuit  
A system clock synchronization circuit according to the present invention includes: a first synchronization and timing delay circuit synchronizing an input clock with a system clock and sending out...
6927604 Clock signal selector circuit with reduced probability of erroneous output due to metastability  
A clock signal selector circuit is disclosed including a synchronizer circuit, two switching circuits, and a multiplexer. The synchronizer circuit synchronizes a first control signal to a first...
6917656 Communications network having a time-controlled communication protocol  
The invention relates to a communications network ( 1 ) comprising a plurality of network nodes ( 2 ), which include each a synchronization circuit ( 5 ) for generating a global clock signal (GT)...
6914945 Clock recovery circuit  
In a clock recovery circuit for DTV using a VSB modulation method, if the frequency of the symbol clock is fs, since the frequency difference between the fs/2 component signal of the VSB signal and...
6912244 Pilot frequency acquisition based on a window of data samples  
Techniques to acquire the frequency of a signal instance based on a window of data samples covering a time period shorter than the time needed to achieve frequency lock. The window of data samples...
6909742 Method and apparatus for reducing interference in a data stream using autocorrelation derived equalization  
Compensating for channel response in communications systems. An equalizing system includes a correlation block to calculate a correlation statistic from a received signal. The correlation statistic...
6907096 Data recovery method and apparatus  
In order to recover phase information, data transmitted at a first frequency is over-sampled using a clock at a second frequency, n times per bit time to obtain n samples. The n samples are used to...
Matches 401 - 450 out of 971 < 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 >