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7349509 Multi rate clock data recovery based on multi sampling technique  
A clock and data recovery device (CDR) based on multi-rate multi-phase oversampling technique is capable of receiving serial data streams of different data rates. The CDR uses a multi-rate...
7349507 Extending PPM tolerance using a tracking data recovery algorithm in a data recovery circuit  
A circuit comprising a sampling logic to sample an incoming signal. A phase detection logic to determine a phase error associated with the sample of the incoming signal and to output an...
7346139 Circuit and method for generating a local clock signal  
A circuit and method for generating a local clock signal and a telecommunications system incorporating the circuit or the method. In one embodiment, the circuit includes: (1) a phase detector for...
7340024 Parallel fractional interpolator with data-rate clock synchronization  
A circuit for single or parallel digital fractional interpolation of data samples has a fractional interpolator filter, an oscillator for outputting timing signals to the fractional interpolator...
7340021 Dynamic phase alignment and clock recovery circuitry  
A dynamic phase alignment circuit is provided that aligns data signals to a phase of a forwarded clock at each channel in a multi-channel communications protocol. A forwarded clock is sent to a...
7336749 Statistical margin test methods and circuits  
Margin-testing circuits and methods rely upon the statistics of sampled data to explore the margin characteristics of received data. One margining circuit samples an incoming data stream N times at...
7336750 Optimal one-shot phase and frequency estimation for timing acquisition  
A method and system for an optimal one-shot estimate of phase and frequency for timing acquisition employ a maximum a posteriori (MAP) formulation to calculate a cost function that is a function of...
7333579 Robust symbol timing recovery circuit for telephone line modem  
A robust symbol timing recovery circuit for a telephone line modem is provided. The symbol timing recovery circuit comprises a timing estimator and an interpolator. The timing estimator, which...
7333578 Linear data recovery phase detector  
An input data sequence is sampled according to a sampling clock such that a first set of samples corresponds to data values and a second set of samples corresponds to edges between the data values....
7333468 Digital phase locked loops for packet stream rate matching and restamping  
A packet stream multiplexer may include one or more control loops (e.g., digital phase locked loops) for tracking the source clock frequency associated with a packet stream. A first control loop...
7330661 Method and apparatus for optical communication between devices  
A method and apparatus for processing a data signal for transmission to a remote device transmits at least two synchronized copies of the data signal, in optical form, in different directions. To...
7321647 Clock extracting circuit and clock extracting method  
In a clock extracting circuit according to the present invention, after serial data is subjected to oversampling using a reference clock of 2N times a frequency of the serial data, clock timing in...
7317775 Switched deskew on arbitrary data  
A method and circuit capable of handling skew between a clock and data signal up to +/− one half bit on a random input data pattern. A digital algorithm cycles through each data bit and...
7317774 Systems and methods for reducing harmonic interference effects in analog to digital conversion  
Systems and methods are described for increasing the effective dynamic range of a digital data stream in a software-defined radio receiver. In one system the sample rate of an analog to digital...
7315596 Interpolator based clock and data recovery (CDR) circuit with digitally programmable BW and tracking capability  
The present invention facilitates clock and data recovery ( 330,716/718 ) for serial data streams ( 317,715 ) by providing a mechanism that can be employed to maintain a fixed tracking capability...
7315583 Digital subscriber line (DSL) modems supporting high-speed universal serial bus (USB) interfaces and related methods and computer program products  
The present invention provides asymmetric digital subscriber line (ADSL) modems including a discrete multitone (DMT) modem module. The DMT modem module includes a digital signal processor (DSP)...
7315594 Clock data recovering system with external early/late input  
The invention is directed to a clock data recovery system for resampling a clock signal to an incoming data signal. The clock data recovery system comprises a clock generator for generating the...
7315598 Data recovery using data eye tracking  
A data recovery system for a serial digital data link includes a data sampler, compare logic, a phase controller, and a phase shifter. The data sampler samples input data three times in a bit time...
7315597 Sampling frequency conversion device and sampling frequency conversion method  
A sampling frequency conversion device comprises an internal circuit for executing in synchronization with an internal clock a signal processing of input data fetched in accordance with an input...
7315593 Hyperfine oversampler method and apparatus  
A plurality of digital samplers operating on a common signal under test (SUT) sample the SUT at a sample rate beyond that which guarantees monotonic sampling and non-overlapping setup and hold...
7313210 System and method for establishing a known timing relationship between two clock signals  
A system and method for establishing a known timing relationship between two clock signals, wherein a first clock signal is operable to clock data transfer operations from a transmitter domain to a...
7313170 Spread spectrum receiver  
A signal generation/noise extraction unit that includes an analog-to-digital converter, a switch, a filter, a subtracter, an oscillator, a multiplier, and a switch generates a down-sampled signal...
7310400 Data recovery device and method  
A data recovery device. The device adjusts a digital signal according to a pulse signal output by a phase-locked loop circuit. The sampling circuit samples each bit of the digital signal five times...
7310397 Data recovery circuit, phase detection circuit and method for detecting and correcting phase conditions  
In the data recovery circuit of the invention, a first group of sampling clock pulses is used for sampling approximately the central portions of the data bits in an incoming data stream to produce...
7308034 Method and device for tracking carrier frequency offset and sampling frequency offset in orthogonal frequency division multiplexing wireless communication system  
A method for tracking carrier frequency and sampling frequency offsets in an OFDM wireless communication system comprises: (a) detecting data received from the transmitter using a first signal, and...
7308620 Method to obtain the worst case transmit data and jitter pattern that minimizes the receiver's data eye for arbitrary channel model  
A serial link system is provided for determining a worst-case cumulative data eye. The system includes a transmitter, a receiver, and a channel between the transmitter and receiver such that data...
7308061 Read channel apparatus and method for an optical storage system  
A read channel apparatus is disclosed for reading data recorded on an optical storage system at a predetermined baud rate. The apparatus asynchronously samples an analog read signal generating from...
7308060 Self correcting data re-timing circuit and method  
An eye opener circuit is provided which performs a data re-timing/eye opening function on a data signal after having been corrupted by jitter. The circuit uses a PLL driven by a clock source which...
7305050 Method and apparatus for processing signals received from a channel having a variable channel length  
A receiver includes a channel length determination unit to determine a channel length for use by a channel estimator. In at least one embodiment, an iterative process is used to find a channel...
7302026 Clock recovery circuit and electronic device using a clock recovery circuit  
A clock recovery circuit includes a phase discriminating circuit for discriminating, at every edge of a received data signal, phase lead or phase lag of an identically directed edge of the clock...
7301996 Skew cancellation for source synchronous clock and data signals  
The skew between a received clock signal and a received data signal that are source synchronous, is accounted for such that stable bit values of the received data signal may be sampled. For...
7298807 Circuit, apparatus and method for adjusting a duty-cycle of a clock signal in response to incoming serial data  
A circuit, apparatus and method for maximizing system margins by adjusting a duty-cycle of a clock signal in a receive circuit to whatever duty-cycle is optimal for the particular incoming serial...
7298772 Packet detection, symbol timing, and coarse frequency estimation in an OFDM communications system  
A integrated system for generation of packet detection, symbol timing, and coarse frequency offset for an orthogonal frequency division multiplexed (OFDM) receiver having a stream of input symbols...
7295641 Phase alignment circuitry and methods  
The phase of a data signal relative to a reference clock signal is approximated relatively accurately using only relatively coarse increments of phase shift between trial version of a sampling...
7295601 Method and apparatus for performing digital timing recovery on oversampled 802.11b baseband signals  
An apparatus and method for performing digital timing recovery includes a rotating demultiplexor receiving a four times oversampled baseband signal and providing four downsampled phases at...
7292668 Data processor and data processing method  
In a data processor, a pickup head reads the data from a memory medium. Such data transferred in a plurality of parallel bits in synchronization with the clock signal to a controller unit from a...
7292670 System and method for automatically correcting duty cycle distortion  
In accordance with the teachings described herein, systems and methods are provided for automatically correcting duty cycle distortion. A slicer may be used to receive a data input signal and...
7292186 Method and system for synchronizing multiple tracking devices for a geo-location system  
A method and system of synchronizing multiple tracking devices in a geo-location receiver system comprising: receiving a first plurality of geo-location signals with a first tracking device; and...
7292662 Feed forward clock and data recovery unit  
Disclosed is a feed forward clock and data recovery unit for recovering a received serial data bit stream having a feed forward phase tracking unit for tracking of a sampling time to the center of...
7292665 Method and apparatus for reception of data over digital transmission link  
An over-sampled sequence detector operates on sampled data and tracks the detection reliability of the sampled data. The detector separately analyzes sample sequences for different sampling phases...
7286625 High-speed clock and data recovery circuit  
A 40-Gb/s clock and data recovery (CDR) circuit incorporates a quarter-rate phase detector and a multi-phase voltage controlled oscillator to re-time and de-multiplex a 40-Gb/s input data signal...
7286444 Method and system for synchronizing separated clocks  
Methods and systems for synchronizing a first clock with a second clock, wherein the clocks are separated, are disclosed. A representative system, among others, includes a correlated particle...
7283595 Ultra wide band pulse train generator  
An ultra wide band (UWB) pulse train generator, which includes a trigger signal controller for sequentially outputting n trigger signals for triggering generation of UWB pulse train in accordance...
7281176 Determining signal quality and selecting a slice level via a forbidden zone  
In one embodiment, a method may determine a number of data transitions occurring in a forbidden zone at each of a first and second slice levels and adjust a slice level offset for an amplifier...
7280628 Data capture for a source synchronous interface  
Method and apparatus for data recapture from a source synchronous interface. A data signal is obtained via the source synchronous interface. A timing signal is obtained via the source synchronous...
7277643 Clock extracting fabric in a communication device  
A signal communication apparatus of a clock reproduction system in which clock signals are extracted from each of parallel data signals for redigitizing each of the data signals. The apparatus...
7274763 Unit for determining the sampling phase  
The invention relates to an apparatus and a method for ascertaining and correcting the optimum sampling time for an oversampled input bit stream. This involves feeding the data bit blanked with the...
7274762 Calculation circuit for calculating a sampling phase error  
A calculation circuit for calculating a sampling phase error is provided. According to one aspect, a calculation circuit includes a first delay element chain having serially connected delay...
7272201 System for synchronous sampling and time-of-day clocking using an encoded time signal  
The system for synchronous sampling uses an encoded time signal, such as an IRIG-B signal. The IRIG-B signal is applied to an edge detector, which produces pulses based on the edges of the encoded...
7272175 Digital phase locked loop  
Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. The invention corrects for carrier and sampling phase errors, as well as...
Matches 201 - 250 out of 968 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >