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7434084 |
Method and apparatus for eliminating sampling errors on a serial bus
A synchronous bit-serial data interface utilizes a transmitter that transmits a data stream having duplicates of each data bit. The receiver samples the data stream utilizing either the rising or...
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7430259 |
Two-wire chip-to-chip interface
A method for communicating data over a serial interface between a master device and at least one slave device is disclosed. A master device generates a preamble that is attached to a data block for...
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7428284 |
Phase detector and method providing rapid locking of delay-lock loops
A delay-lock loop includes a dual mode phase detector. The dual mode phase detector includes a single edge phase detector that generates output signals indicative of the phase relationship between...
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7428283 |
Data recovery algorithm using data position detection and serial data receiver adopting the same
The present invention relates generally to a data recovery algorithm and a serial link data receiver adopting the same. The data recovery algorithm includes receiving a serial data stream and a...
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7428282 |
Timing recovery of PAM signals using baud rate interpolation
A timing recovery method enables interpolation of PAM signals sampled at baud rate. The method exploits the structure of the PAM signal and also the smoothness of the channel pulse response. The...
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7428274 |
Receiver of frequency-modulated signals with digital demodulator
A receiver of a frequency-modulated signal representing a digital signal includes a down conversion unit or frequency translation unit to lower the frequency of the frequency-modulated signal and a...
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7426251 |
High speed transceiver operable to receive lower data rate transmissions
A high speed transceiver operable to receive lower data rate transmissions includes an oversampling module and a data recovery system. The oversampling module is operably coupled to oversample a...
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7426252 |
High speed transceiver receiving lower rate data
A high speed transceiver operable to receive lower data rate transmissions includes an oversampling module, an aligning module, a selecting module, and a memory module. The oversampling module is...
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7424275 |
Method and system for sampling a signal
A system includes a digital circuit that may be clocked by a digital clock signal having an associated clock period. The system also includes a sample clock generation circuit coupled to a sampling...
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7424046 |
Spread spectrum clock signal generation system and method
A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a...
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7421049 |
Apparatus and method for automated determination of sampling phase of an analog video signal
A method and an apparatus provide extraction of data from an analog signal. The method includes deriving a data-location signal having amplitude transitions that identify a phase of amplitude...
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7421050 |
Parallel sampled multi-stage decimated digital loop filter for clock/data recovery
The present invention utilizes a parallel sampled multi stage decimated digital loop filter for clock and data recovery function. In particular, the present invention provides multiple sampling...
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7418068 |
Data capture technique for high speed signaling
A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock...
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7415059 |
Method and system for fast timing recovery for preamble based transmission systems
Using a combination of auto-correlation and cross-correlation techniques provides a symbol timing recovery in a Wireless Local Area Network (WLAN) environment that is extremely robust to wireless...
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7415089 |
High-speed serial link clock and data recovery
A system for clock and data recovery (“CDR”) includes a clock generator, a half-rate phase detector for receiving the input data, an encoder, a phase selector outputting recovered clock, a...
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7414550 |
Methods and systems for sample rate conversion and sample clock synchronization
The architecture for a combined universal sample rate converter and a sample clock synchronizer is presented. The universal sample rate converter can be applied, for example, to audio samples...
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7415090 |
Method and device for loop timing recovery based on maximum constellation signal
A receiving device of a multiple communications channel system includes: a noise detector that detects channel noise among the received data signals and selects at least one channel among a...
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7415088 |
Multi-standard baseband receiver
Techniques for processing incoming signals conforming to a plurality of standards or communication formats with a single baseband receive section are disclosed. In one aspect, a plurality of analog...
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7412016 |
Data-level clock recovery
A circuit for adjusting the phase of a clock signal. A first sampling circuit generates a sequence of data samples in response to transitions of the clock signal, each of the data samples having...
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7411531 |
Methods and apparatus for asynchronous sampling of a received signal at a downsampled rate
Methods and apparatus are provided for decimated interpolated clock/data recovery (ICDR) to perform asynchronous sampling of a received signal. A received signal is converted to a plurality of...
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7412017 |
Method and apparatus for reception of data over a transmission link
An over-sampled sequence detector operates on sampled data and tracks the detection reliability of the sampled data. The detector separately analyzes sample sequences for different sampling phases...
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7408916 |
Synchronisation of frame transmissions in a telecommunications network
The invention concerns a method for synchronising clocks of base transceiver stations in a telecommunications system and a mobile communications system. According to the invention, in either some...
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7406142 |
Data recovery circuits using oversampling for best data sample selection
An improved data recovery circuit based on an oversampling technique to select the best data sample to be kept as the data to recover that is only based on accumulating the data edges (or...
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7403582 |
Serial communication device
The invention is a serial communication device for receiving serial data and sampling the serial data with synchronizing with communication clocks. The device has a clock generation unit for...
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7403545 |
Radio communication system and apparatus
A radio communication system for transmitting a radio signal with a transmission format in which a channel response calculation preamble signal serving as a reference upon reception is inserted is...
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7403580 |
Software defined radio system
The invention provides a technique that saves rate conversion accompanying complicated calculations and shares an analog filter for anti-aliasing in a sampling device. The sampling device employs...
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7400180 |
Semiconductor device having input circuits activated by clocks having different phases
Input circuits connected to an external input terminal PAD via resistor elements are activated in response to the level transition of the clock signals supplied thereto for accepting input signals....
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7397876 |
Methods and arrangements for link power reduction
Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data...
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7397875 |
Method of synchronising data
A method of synchronizing data in a communications system includes generating a composite signal comprising a serial stream of data partitioned in one or more frames, and transmitting the composite...
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7391837 |
Newton's method-based timing recovery circuit
A Newton's method-based timing recovery circuit is provided for to solving a polynomial accurately. The timing recovery circuit can generate an interpolation signal, whose timing errors are...
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7388931 |
ADC architecture for wireless applications
A simplified architecture is disclosed for ADC conversion of received in-phase I and quadrature Q signals. Circuit area is substantially reduced by sharing a single ADC to convert both signals,...
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7386080 |
High-speed data sampler for optical interconnect
A system and method for sampling a data stream generates a number of clock signals having equally spaced phases and then samples a data stream using the clock signals. The clock phases are...
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7386406 |
Forced-alignment measurement tools for composite eye diagrams
An original composite eye diagram is reformulated by deliberately re-aligning its component eye diagrams according to some appropriate standard. This ‘forced-alignment’ shifts the components in...
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7386081 |
Timing control circuit and method thereof
A timing control circuit includes a synchronous detecting portion which detects a synchronous pattern data of a received signal which has been demodulated based on a first control signal and...
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7382837 |
Apparatus and method for estimating a decision boundary in symbol units in a mobile communication system
An apparatus and method for estimating a decision boundary in symbol units in a mobile communication system. The method for estimating a decision boundary of reception symbols in a receiver of a...
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7376189 |
Remote control signal reception circuit, remote control signal reception method, remote control signal reception program, and computer-readable storage medium storing the program
The subject invention provides a remote control signal reception circuit that carries out quantization of an input data signal 101 by sampling the signal with a first sampling frequency that is...
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7376211 |
High speed early/late discrimination systems and methods for clock and data recovery receivers
The present invention facilitates clock and data recovery for serial data streams by providing a mechanism that can be employed to detect and adjust operation and timing of clocks. The invention...
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7366254 |
Edge incremental redundancy support in a cellular wireless terminal
A system for implementing Incremental Redundancy (IR) operations in a wireless receiver includes a baseband processor, an equalizer, a system processor, and an IR processing module. The baseband...
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7366224 |
System and method for the detection of presence of a signal and its synchronization, for a frequency hopping system working in a disturbed environment
A method and device are disclosed for the detection and synchronization of a signal in a frequency-hopping system. The method has a step, for each frequency F( 1 ) . . . F(M), of selecting the K...
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7363269 |
Conversational dealing system
A conversational trading system allows a plurality of instruments, for example financial instruments such as foreign exchange products to be traded from a single user interface. The interface...
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7362836 |
Method for selecting optimum sampling parameters for a plurality of data receivers having at least one sampling parameter in common
Eye diagrams are made for signals on each channel in a group thereof. Outlying signals that do not exhibit overlap for a sampling parameter that is to be common for all channels may be ignored and...
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7362812 |
Channel tracking using step size based on norm-1 based errors across multiple OFDM symbols
A channel tracking module, configured for generating updated equalization coefficients for a frequency equalizer, is configured for determining a digital-based error value between equalized signals...
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7362834 |
Method and device for synchronizing at least one node of a bus system and a corresponding bus system
Method of synchronizing at least one user of a bus system which is operated with a preselectable system clock period (NTU), a local clock period (LNTU) and a reference clock period (GNTU) being...
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7359468 |
Apparatus for synchronizing clock and data between two domains having unknown but coherent phase
A data synchronizer is provided for synchronizing data across two different clock domains in a manner that avoids additive jitter. The data synchronizer includes a synchronizer inputting a sampling...
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7359469 |
Signal delaying device and method for dynamic delaying of a digitally sampled signal
A signal delaying device ( 1 ) for the dynamic delaying of a digitally sampled input signal comprises a memory element ( 2 ) and a series-connected interpolation element ( 3 ). According to the...
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7358781 |
Automation device with stored profile
The invention relates to an automation device, in which a multiplicity of physically distributed functional units communicate with each other by means of a common transmission protocol. The device...
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7359429 |
Support of the determination of a correlation
A method for supporting a determination of the correlation between at least one received code modulated signal and at least one available replica code is shown. In order to reduce the total memory...
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7356106 |
Clock and data recovery circuit
A clock and data recovery (CDR) circuit comprises a phase detector (PD) and a quadrature phase (QP) detector. A frequency detector (FD) is coupled to the PD and QP detector. The FD detects...
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7356107 |
Flying-adder frequency synthesizer-based digital-controlled oscillator and video decoder including the same
A video decoder ( 52, 152 ) including a digital-control oscillator (DCO) ( 60, 160 ) is disclosed. The DCO ( 60, 160 ) includes a first flying-adder frequency synthesis circuit ( 74 S) that...
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7352815 |
Data transceiver and method for equalizing the data eye of a differential input data signal
Apparatus and method for counteracting high frequency attenuation of a differential input data signal as the signal is conducted through a data link. A differential input data signal is transmitted...
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