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6917656 |
Communications network having a time-controlled communication protocol
The invention relates to a communications network ( 1 ) comprising a plurality of network nodes ( 2 ), which include each a synchronization circuit ( 5 ) for generating a global clock signal (GT)...
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6914945 |
Clock recovery circuit
In a clock recovery circuit for DTV using a VSB modulation method, if the frequency of the symbol clock is fs, since the frequency difference between the fs/2 component signal of the VSB signal and...
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6912244 |
Pilot frequency acquisition based on a window of data samples
Techniques to acquire the frequency of a signal instance based on a window of data samples covering a time period shorter than the time needed to achieve frequency lock. The window of data samples...
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6909742 |
Method and apparatus for reducing interference in a data stream using autocorrelation derived equalization
Compensating for channel response in communications systems. An equalizing system includes a correlation block to calculate a correlation statistic from a received signal. The correlation statistic...
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6907096 |
Data recovery method and apparatus
In order to recover phase information, data transmitted at a first frequency is over-sampled using a clock at a second frequency, n times per bit time to obtain n samples. The n samples are used to...
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6901126 |
Time division multiplex data recovery system using close loop phase and delay locked loop
A time division multiplex data recovery system using a closed-loop phase lock loop (PLL) and delay locked loop (DLL) is disclosed. In other words, one closed loop comprises both a phase locked loop...
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6895062 |
High speed serial interface
A high speed serial interface system that compensates for phase drift by over sampling received data packets. The system utilizes a transmitter and receiver that operate within the same clock...
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6895310 |
Vehicle related wireless scientific instrumentation telematics
An in-vehicle device data communicates with data processing resources, including global network based data processing resources for the purpose of programming and receiving data from an in-vehicle...
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6891906 |
Demodulator, clock recovery circuit, demodulation method and clock recovery method
A demodulator is constituted by: a clock recovery circuit for generating a recovered clock from the series of received data and outputting the recovered clock; a state estimation circuit for making...
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6891910 |
Baud-rate timing recovery
A system and a method for simple and robust baud-rate timing recovery suitable for jointly operating with a decision-feedback equalizer are disclosed. Timing functions for timing recovery are...
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6888906 |
Clock and data regenerator with demultiplexer function
Clock and data regenerator with demultiplexer function wherein the clock and phase generator operates with four sampling flip-flops whose output signals are compared with one another with the aid...
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6888886 |
Interface apparatus and method for receiving serially-transmitted data
Serially transmitted digital data are received in a predetermined format such as an SPDIF format. In the format, identification data are incorporated in the serial data in predetermined cycles....
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6888790 |
Frame synchronization technique for OFDM based modulation scheme
The present invention relates to the field of communications. The method includes generating a sequence of symbols, the sequence of symbols including preamble symbols and a data symbol. The method...
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6888905 |
Low deviation index demodulation scheme
A wireless receiver e.g., a Bluetooth-compatible receiver or a receive chain in a Bluetooth-compatible transceiver, includes a discriminator unit and a timing recovery unit. The output of the...
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6880097 |
Method and device for checking the synchronization between two nodes Ni-1, Ni in a network
The invention concerns a method of checking the synchronization between at least two nodes Ni−1, Ni, with i=1, . . . , n in a network, each of said nodes having respectively an internal clock...
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6879629 |
Method and apparatus for enhanced timing loop for a PRML data channel
Methods and apparatus for enhanced timing loop are provided for a partial-response maximum-likelihood (PRML) data channel in a direct access storage device (DASD). An acquisition timing circuit for...
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6879650 |
Circuit and method for detecting and correcting data clocking errors
In a communications environment wherein data terminal equipment (DTE) transmits a data signal to data communication equipment (DCE) synchronously with a clocking signal provided by the DCE to the...
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6876696 |
Timing device and method using a timing equalizer filter for a digital communications systems
A method of training and operating a dual-duplex, four-wire communications system to provide for time alignment in the receivers of data that is time aligned in the transmitters, even in the...
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6873666 |
Circuit and method for symbol timing recovery in phase modulation systems
The present invention relates to a circuit and method for symbol timing recovery in phase modulation systems. First, phase differences of in-phase signals and quadrature signals in a polar...
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6874097 |
Timing skew compensation technique for parallel data channels
A method and apparatus for correcting the timing skew of data signals in a parallel data transmission system, such as Small Computer System Interface (SCSI) data bus, relative to a receive clock in...
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6870876 |
Method for sending information in a telecommunication system
The invention is concerned with a method and an apparatus, wherein information data is sent between at least two transceivers in a telecommunication system. The information data is transmitted from...
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6868120 |
Real-time system for measuring the Ricean K-factor
A system and method for measuring the Ricean K-factor of a wireless channel in real time are provided. An amplitude sample of a transmitted RE waveform of either fixed or varying amplitude is...
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6868127 |
Signal receiving circuit and signal receiving method
A signal receiving circuit receives sample data without an occurrence of discontinuity in the received sample data, even if the number of sample data to be transmitted from a transmitting terminal...
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6865175 |
Method and configuration for transmitting data over a radio interface in a radio communications system
A method and a configuration for transmitting data over a radio interface which is organized into timeslots with finite radio blocks in accordance with a TDMA subscriber separation method are...
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6856648 |
Method and apparatus for equalizer updating and sampling rate control
Equalizer updating and accurate sampling rate control in a DMT receiver are simultaneously performed using a known signal, such as a pilot tone. The known signal is separated into its real and...
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6856659 |
Clock recovery method in digital signal sampling
A clock recovery method in digital signal sampling wherein the clock is generated from a phase-locking loop or PLL which multiples a given frequency by a whole number. The method includes comparing...
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6856658 |
Digital PLL circuit operable in short burst interval
A digital PLL (phase locked loop) circuit includes a sampling circuit, a plurality of internal circuits and an output switching circuit. The sampling circuit samples a burst data signal in response...
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6850709 |
Apparatus and method for improved connectivity in wireless optical communication systems
The present invention provides an apparatus and a method for improved connectivity in wireless optical networks. Therefore at least two or more receiving units are used which receive an infrared...
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6850576 |
Method and apparatus for reproducing timing, and a demodulating apparatus that uses the method and apparatus for reproducing timing
A base band signal is sampled, based on an asynchronous sampling clocking, to output two sampled data series. A transmission side complex symbol frequency generator generates a complex transmission...
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6850581 |
Timing circuit
Disclosed is a timing circuit for generating a clock signal which indicates a timing for discriminating a data signal. The timing circuit includes a branching circuit for branching a data signal in...
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6850583 |
Clock generation apparatus
A clock generation apparatus generates a synchronous clock based on an input analog signal. The average of maximum and minimum values of a digital signal in a predetermined period is used as a...
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6847693 |
Method and device providing data derived timing recovery for multicarrier communications
A method and a device for providing timing recovery in a multicarrier transmission system is provided. The data derived timing recovery apparatus with the timing error controller adjusts the...
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6842488 |
VSB/QAM receiver and method
A vestigial sideband/quadrature amplitude modulation (VSB/QAM) receiver, which receives both VSB and QAM signals and restores a carrier wave with a restored symbol clock after restoring a symbol...
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6841983 |
Digital signal to pulse converter and method of digital signal to pulse conversion
A digital signal to pulse converter including a spectral spreader which provides an adjusted clock signal that does not cycle during selected cycles. The adjusted clock signal is written into a...
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6839659 |
System and method for acquiring data
A system for acquiring, and displaying, data such as physiological data, from a plurality of data connection devices, each of which monitor one or more different parameters and output data at...
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6832332 |
Automatic detection and correction of marginal data in polling loop system
Provided is a system and method for detecting marginal data transmissions from any of a number of security devices in a security system including a control unit in communication with the security...
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6831958 |
Timing recovery device using a fixed equalizer
The present invention relates to a receiving system (R) including an adaptive first equalizer (E 1 ) associated with a first threshold detector (S 1 ), and a device (TR) which enables the timing...
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6829316 |
Input circuit and output circuit
An input circuit includes: a comparator; first and second delay circuits; a selector; an input buffer; and a holding circuit. The comparator compares the leading and/or trailing edges of a data...
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6829304 |
Method for clock recovery in MPEG systems
A method for clock recovery comprises a series of steps to be performed in a decoder to adaptively estimate the ratio P/S of the frequency of an encoder system time clock and the frequency of a...
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6823001 |
Dual stage communication processor
A communications processor is presented that is capable of receiving a potentially degraded data transmission signals operating at high transmission rates and generating an improved data...
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6813325 |
System and method to reduce transmit wander in a digital subscriber line
A system and method for reducing transmit carrier wander in a DSL communication system are disclosed. A network timing reference unit provides an automatic embedded solution for synchronizing DSL...
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6801592 |
Method and a circuit for retiming a digital data signal
By application of a method and a circuit for retiming one or several digital data signal(s) (D in ) each consisting of a number of successive bits, wherein the data signal is sampled by an internal...
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6795515 |
Method and apparatus for locating sampling points in a synchronous data stream
An apparatus and process for updating a sample time in a serial link which converts serial data in parallel data. A delay line stores multiple samples of at least two data bits received over the...
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6795514 |
Integrated data clock extractor
A circuit for extracting a data clock signal from an input data stream, comprising a programmable delay element for receiving an arbitrary clock signal, delaying the arbitrary clock signal by a...
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6795492 |
Configurable exciter
An exciter ( 10 ) is located along an information stream path of a transmission system ( 12 ). The exciter ( 10 ) supplies an information signal as a drive to an amplifying arrangement ( 14 ). A...
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6791363 |
Multistage, single-rail logic circuitry and method therefore
According to one form of the invention, an apparatus includes first timing circuitry, at least one stage of logic circuitry and second timing circuitry. The first timing circuitry has a first data...
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6792060 |
Processor having an adaptable operational frequency
The invention relates to a processing device for digital data which is capable of processing data which have been sampled with a sampling clock which may have any value whatsoever with respect to...
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6792059 |
Early/on-time/late gate bit synchronizer
A bit synchronizer for a digital receiver system accounts for loss of bit synchronization due to transmission phenomena. The bit synchronizer includes a DC level estimator for converting a sampled...
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6792036 |
Method for estimating channel impulse responses of a mobile radio channel
A method is described for estimating channel impulse responses of a mobile radio channel with a broad bandwidth by a code division multiplexing method, and with a synchronization channel...
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6782068 |
PLL lockout watchdog
A circuit that may be configured to detect a lockout condition of a phase lock loop (PLL) circuit. The circuit may be configured to forcibly correct an operating frequency of the PLL circuit.
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